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2012 12th Annual Non-Volatile Memory Technology Symposium Proceedings ,
1
Modeling and test for parasitic resistance and capacitance ..:
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Proceedings of the 2005 Asia and South Pacific Design Automation Conference ,
2
Oscillation ring based interconnect test scheme for SOC:
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Proceedings of the conference on European design automation ,
3
SEESIM—a fast synchronous sequential circuit fault simulato..:
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Proceedings of the 27th ACM/IEEE Design Automation Conference ,
4
A parallel pattern mixed-level fault simulator:
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Proceedings of the 28th ACM/IEEE Design Automation Conference ,
5
A probabilistic testability measure for delay faults:
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Proceedings of the Conference on Design, Automation and Test in Europe ,
6
Modeling and testing of interference faults in the nano NAN..:
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Proceedings of the 2006 Asia and South Pacific Design Automation Conference ,
7
IEEE standard 1500 compatible interconnect diagnosis for de..:
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Proceedings of the 2005 international workshop on System level interconnect prediction ,
8
Multilevel full-chip routing with testability and yield enh..:
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Proceedings of the 2001 Asia and South Pacific Design Automation Conference ,
9
A computer aided engineering system for memory BIST:
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Proceedings of the conference on Design, automation and test in Europe ,
10
All digital built-in delay and crosstalk measurement for on..:
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Proceedings of the Fourth Asian Test Symposium ,
11
Fanout fault analysis for digital logic circuits:
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2008 IEEE International Symposium on Circuits and Systems (ISCAS) ,
12
A reconfigurable MAC architecture implemented with mixed-Vt..:
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Proceedings of the 14th ACM/IEEE International Conference on Human-Robot Interaction ,
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