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Proceedings of the 9th International Workshop on Network on Chip Architectures ,
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Reliability-Aware Task Scheduling using Clustered Replicati..:
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Proceedings of the 2012 Interconnection Network Architecture: On-Chip, Multi-Chip Workshop ,
2
A novel graceful degradable routing algorithm for 3D on-chi..:
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Proceedings of the Conference on Design, Automation and Test in Europe ,
3
An architecture-level approach for mitigating the impact of..:
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Proceedings of the conference on Design, automation and test in Europe ,
4
Scalable architecture for on-chip neural network training u..:
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2008 IEEE International Symposium on Circuits and Systems (ISCAS) ,
5
Co-evolutionary reliability-oriented high-level synthesis:
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2008 IEEE International Symposium on Circuits and Systems (ISCAS) ,
6
A 65nm 10GHz pipelined MAC structure:
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Proceedings of the 17th ACM Great Lakes symposium on VLSI ,
7
Co-evolutionary high-level test synthesis:
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Proceedings of the 17th ACM Great Lakes symposium on VLSI ,
8
HW/SW partitioning using discrete particle swarm:
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Analytic Hierarchy Process with Fuzzy Sets Extensions; Studies in Fuzziness and Soft Computing ,
9
Circular Intuitionistic Fuzzy AHP: An Application in Manufa..:
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Leveraging Applications of Formal Methods, Verification and Validation. Modeling; Lecture Notes in Computer Science ,
10
Program Correctness by Transformation:
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