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Das, Debesh K
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1

Power-aware partitioning and test time reduction for 3D-SoC:

Banerjee, Sabyasachee ; Majumder, Subhashis ; Bhattacharya, Bhargab B..
Innovations in Systems and Software Engineering.  20 (2022)  3 - p. 485-498 , 2022
Link: https://doi.org/10.1007/..
 
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2

Fast algorithms for test optimization of core based 3D SoC:

Banerjee, Sabyasachee ; Majumder, Subhashis ; Das, Debesh K..
Integration.  77 (2021)  - p. 70-88 , 2021
Link: https://doi.org/10.1016/..
 
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3

An iterative structure for synthesizing symmetric functions..:

Deb, Arighna ; Das, Debesh K.
Microprocessors and Microsystems.  53 (2017)  - p. 157-167 , 2017
Link: https://doi.org/10.1016/..
 
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4

Reversible synthesis of symmetric functions with a simple r..:

Deb, Arighna ; Das, Debesh K. ; Rahaman, Hafizur.... (2016)  - p. 1-29
Link: http://dx.doi.org/10.114..
 
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5

Reversible Synthesis of Symmetric Functions with a Simple R..:

Deb, Arighna ; Das, Debesh K. ; Rahaman, Hafizur...
ACM Journal on Emerging Technologies in Computing Systems (JETC).  12 (2016)  4 - p. 1-29 , 2016
Link: https://dl.acm.org/doi/1..
 
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6

Reversible Synthesis of Symmetric Functions with a Simple R..:

Deb, Arighna ; Das, Debesh K. ; Rahaman, Hafizur...
ACM Journal on Emerging Technologies in Computing Systems.  12 (2016)  4 - p. 1-29 , 2016
Link: https://doi.org/10.1145/..
 
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7

Derivation of test set for detecting multiple missing-gate ..:

Kole, Dipak K. ; Rahaman, Hafizur ; Das, Debesh K..
Computers & Electrical Engineering.  39 (2013)  2 - p. 225-236 , 2013
Link: https://doi.org/10.1016/..
 
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8

Fault diagnosis in reversible circuits under missing-gate f..:

Rahaman, Hafizur ; Kole, Dipak K. ; Das, Debesh K..
Computers & Electrical Engineering.  37 (2011)  4 - p. 475-485 , 2011
Link: https://doi.org/10.1016/..
 
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9

Testable design of AND–EXOR logic networks with universal t..:

Rahaman, Hafizur ; Das, Debesh K. ; Bhattacharya, Bhargab B.
Computers & Electrical Engineering.  35 (2009)  5 - p. 644-658 , 2009
Link: https://doi.org/10.1016/..
 
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10

Implementing Symmetric Functions with Hierarchical Modules ..:

Rahaman, Hafizur ; Das, Debesh K. ; Bhattacharya, Bhargab B.
Journal of Electronic Testing.  22 (2006)  2 - p. 125-142 , 2006
Link: https://doi.org/10.1007/..
 
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11

A Degree-of-Freedom Based Synthesis Scheme for Sequential M..:

Sikdar, Biplab K. ; Roy, S. ; Das, Debesh K.
Journal of Electronic Testing.  21 (2005)  1 - p. 83-93 , 2005
Link: https://doi.org/10.1007/..
 
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12

Universal and robust testing of stuck-open faults in Reed–M..:

Das, Debesh K. ; Chakraborty, Susanta ; Bhattacharya, Bhargab B.
International Journal of Electronics.  90 (2003)  1 - p. 1-11 , 2003
Link: https://doi.org/10.1080/..
 
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13

BIST design for detecting multiple stuck-open faults in CMO..:

Rahaman, Hafizur ; Das, Debesh K. ; Bhattacharya, Bhargab B.
Journal of Computer Science and Technology.  17 (2002)  6 - p. 731-737 , 2002
Link: https://doi.org/10.1007/..
 
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14

Logical redundancies in irredundant combinational circuits:

Chakraborty, Susanta ; Das, Debesh K. ; Bhattacharya, Bhargab B.
Journal of Electronic Testing.  4 (1993)  2 - p. 125-130 , 1993
Link: https://doi.org/10.1007/..
 
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15

Irredundant binate realizations of unate functions:

DAS, DEBESH K. ; CHAKRABORTY, SUSANTA ; BHATTACHARYA, BHARGAB B.
International Journal of Electronics.  75 (1993)  1 - p. 65-73 , 1993
Link: https://doi.org/10.1080/..
 
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