E-LIB Suche - Ergebnisse für: Anita Angeline, A

1

Design and evaluation of low power and area efficient appro..:

Gundavarapu, Vishal ; Gowtham, P. ; Anita Angeline, A..
Microprocessors and Microsystems. 106 (2024) - p. 105036 , 2024

Link: https://doi.org/10.1016/..

2

Circuit Techniques for High Performance in CDDK Domino Logi:

, In: 2024 IEEE 4th International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI SATA),

Arun, V ; Kumar, Himanshu ; P, H Sasipriya. - p. 1-4 , 2024

Link: https://doi.org/10.1109/..

3

Design and Evaluation of Low Power Error Tolerant Adder:

, In: 2023 International Conference on Next Generation Electronics (NEleX),

NA, Rishikumar ; A, Anita Angeline ; P, Sasipriya - p. 1-6 , 2023

Link: https://doi.org/10.1109/..

4

Design and Characterization of Standard Cell Libraries for ..:

, In: 2023 Innovations in Power and Advanced Computing Technologies (i-PACT),

M, Murali Krishnan ; A, Anita Angeline ; P, Sasipriya - p. 1-5 , 2023

Link: https://doi.org/10.1109/..

5

Design of Approximate Restoring Dividers for Error Resilien..:

Gowtham, P ; Sasipriya, P ; Anita Angeline, A
ECS Transactions. 107 (2022) 1 - p. 13675-13686 , 2022

Link: https://doi.org/10.1149/..

6

TEL Based Pre-Scaler Design:

, In: 2022 IEEE Delhi Section Conference (DELCON),

Pal, Srijani ; Salimath, Divya S ; Sarkar, Kuntal... - p. 1-5 , 2022

Link: https://doi.org/10.1109/..

7

Design and Evaluation of Error Tolerant Booth Multipliers f..:

, In: 2022 4th International Conference on Smart Systems and Inventive Technology (ICSSIT),

Sanjana, Patri ; Ramesh, Mehana ; Kale, Anushka.. - p. 1414-1418 , 2022

Link: https://doi.org/10.1109/..

8

Low Power Memory System Design Using Power Gated SRAM Cell:

Pal, Srijani ; Salimath, Divya S ; Chandran, Banusha..
IOP Conference Series: Materials Science and Engineering. 1187 (2021) 1 - p. 012008 , 2021

Link: https://doi.org/10.1088/..

9

High Performance Wallace Tree Multiplier Using Majority Gat..:

Mummudi Murasu, M ; Sujith, Sanjana ; Anita Angeline, A..
IOP Conference Series: Materials Science and Engineering. 1187 (2021) 1 - p. 012003 , 2021

Link: https://doi.org/10.1088/..

10

Design of energy efficient carry lookahead adder using nove..:

Bhalerao, Abhishek L ; Mane, Aishwarya ; Pensenwar, Kartik...
Journal of Physics: Conference Series. 1716 (2020) 1 - p. 012033 , 2020

Link: https://doi.org/10.1088/..

11

Design of Arithmetic Logic Unit using Pseudo Dynamic Buffer..:

Kushal Kumar, S V ; Anita Angeline, A.
Journal of Physics: Conference Series. 1716 (2020) 1 - p. 012034 , 2020

Link: https://doi.org/10.1088/..

12

Schmitt Trigger Designs Using Domino Logic Style:

Singh, Nikhil ; Shekhar, Siddharth ; Angeline, Anita.
ECS Transactions. 107 (2022) 1 - p. 8885-8896 , 2022

Link: https://doi.org/10.1149/..

13

Transmission Gate based Keeper Control for Domino Logic Cir..:

, In: Proceedings of the 2022 Fourteenth International Conference on Contemporary Computing,

Rout, Ansuman ; DN, Sagar ; Angeline, Anita. - p. 673-678 , 2022

Link: https://dl.acm.org/doi/1..

14

Domino Logic Keeper Circuit Design Techniques: A Review:

Angeline, A. Anita ; Bhaaskaran, V. S. Kanchana
Journal of The Institution of Engineers (India): Series B. 103 (2021) 2 - p. 669-679 , 2021

Link: https://doi.org/10.1007/..

15

Speed enhancement techniques for Clock-Delayed Dual Keeper ..:

Angeline, A. Anita ; Bhaaskaran, V.S. Kanchana
International Journal of Electronics. 107 (2020) 8 - p. 1239-1253 , 2020

Link: https://doi.org/10.1080/..