Asada, Kunihiro
118  Ergebnisse:
Personensuche X
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1

4-Cycle-Start-Up Reference-Clock-Less Digital CDR Utilizing..:

IIZUKA, Tetsuya ; CHIN, Meikan ; NAKURA, Toru.
IEICE Transactions on Electronics.  E105.C (2022)  10 - p. 544-551 , 2022
 
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2

Spatial resolution improvement for point light source detec..:

Iizuka, Tetsuya ; Xu, Kai ; Yang, Xiao..
IEICE Electronics Express.  16 (2019)  19 - p. 20190390-20190390 , 2019
 
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3

A 16-bit 2.0-ps Resolution Two-Step TDC in 0.18-$\mu$ m CMO..:

Enomoto, Ryuichi ; Iizuka, Tetsuya ; Koga, Takehisa..
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  27 (2019)  1 - p. 11-19 , 2019
 
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4

A 65 nm CMOS Synthesizable Digital Low-Dropout Regulator Ba..:

, In: VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms; IFIP Advances in Information and Communication Technology,
Ojima, Naoki ; Nakura, Toru ; Iizuka, Tetsuya. - p. 1-13 , 2019
 
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5

Triangular Active Charge Injection Method for Resonant Powe..:

KANO, Masahiro ; NAKURA, Toru ; IIZUKA, Tetsuya.
IEICE Transactions on Electronics.  E101.C (2018)  4 - p. 292-298 , 2018
 
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6

Analysis and design of impulse signal generator based on cu..:

Kanjanavirojkul, Parit ; Mai-Khanh, Nguyen Ngoc ; Iizuka, Tetsuya..
Analog Integrated Circuits and Signal Processing.  97 (2018)  3 - p. 457-470 , 2018
 
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7

Digitally-Controlled Compensation Current Injection to ATE ..:

Terao, Naoki ; Nakura, Toru ; Ishida, Masahiro...
Journal of Electronic Testing.  34 (2018)  2 - p. 147-161 , 2018
 
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8

Quick-Start Pulse Width Controlled PLL with Frequency and P..:

NAKURA, Toru ; KAGAYA, Tsukasa ; IIZUKA, Tetsuya.
IEICE Transactions on Electronics.  E101.C (2018)  4 - p. 218-223 , 2018
 
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9

Optimal Design Method of Sub-Ranging ADC Based on Stochasti..:

HOSSAIN, Md. Maruf ; IIZUKA, Tetsuya ; NAKURA, Toru.
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences.  E101.A (2018)  2 - p. 410-424 , 2018
 
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10

Time-domain approach for analog circuits in deep sub-micron..:

Asada, Kunihiro ; Nakura, Toru ; Iizuka, Tetsuya.
IEICE Electronics Express.  15 (2018)  6 - p. 20182001-20182001 , 2018
 
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11

A PLL Compiler from Specification to GDSII:

NAKURA, Toru ; IIZUKA, Tetsuya ; ASADA, Kunihiro
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences.  E100.A (2017)  12 - p. 2741-2749 , 2017
 
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12

A Gate Delay Mismatch Tolerant Time-Mode Analog Accumulator..:

YANO, Tomohiko ; NAKURA, Toru ; IIZUKA, Tetsuya.
IEICE Transactions on Electronics.  E100.C (2017)  9 - p. 736-745 , 2017
 
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13

Design, Analysis and Implementation of Pulse Generator by C..:

KANJANAVIROJKUL, Parit ; NGOC MAI-KHANH, Nguyen ; IIZUKA, Tetsuya..
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences.  E100.A (2017)  1 - p. 200-209 , 2017
 
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14

A CMOS Broadband Transceiver with On-Chip Antenna Array and..:

NGOC MAI-KHANH, Nguyen ; ASADA, Kunihiro
IEICE Transactions on Electronics.  E100.C (2017)  12 - p. 1078-1086 , 2017
 
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15

A 15 × 15 single photon avalanche diode sensor featuring br..:

Yang, Xiao ; Zhu, Hongbo ; Nakura, Toru..
Japanese Journal of Applied Physics.  55 (2016)  4S - p. 04EF04 , 2016
 
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