E-LIB Suche - Ergebnisse für: Béchennec, Jean-Luc

1

SCHEMATIC: Compile-Time Checkpoint Placement and Memory All..:

, In: 2024 IEEE/ACM International Symposium on Code Generation and Optimization (CGO),

Reymond, Hugo ; Bechennec, Jean-Luc ; Briday, Mikael... - p. 258-269 , 2024

Link: https://doi.org/10.1109/..

2

Formal verification process of the compliance of a multicor..:

Haur, Imane ; Béchennec, Jean-Luc ; H. Roux, Olivier
Software Quality Journal. 31 (2023) 2 - p. 497-531 , 2023

Link: https://doi.org/10.1007/..

3

Model-Checking of Concurrent Real-Time Software Using High-..:

Haur, Imane ; Béchennec, Jean-Luc ; Roux, Olivier H.
Cybernetics and Systems. , 2023

Link: https://doi.org/10.1080/..

4

High-level Colored Time Petri Nets for true concurrency mod..:

, In: 2022 8th International Conference on Control, Decision and Information Technologies (CoDIT),

Haur, Imane ; Bechennec, Jean-Luc ; Roux, Olivier H. - p. 21-26 , 2022

Link: https://doi.org/10.1109/..

5

Cost-optimal timed trace synthesis for scheduling of interm..:

Bernabeu, Antoine ; Béchennec, Jean-Luc ; Briday, Mikael..
Discrete Event Dynamic Systems. 33 (2022) 1 - p. 63-93 , 2022

Link: https://doi.org/10.1007/..

6

Formal Verification of the Inter-core Synchronization of a ..:

, In: Formal Methods and Software Engineering; Lecture Notes in Computer Science,

Haur, Imane ; Béchennec, Jean-Luc ; Roux, Olivier H. - p. 140-155 , 2022

Link: https://doi.org/10.1007/..

7

Energy Efficiency is Not Enough:Towards a Batteryless Inter..:

, In: Audio Mostly 2021,

Lostanlen, Vincent ; Bernabeu, Antoine ; Béchennec, Jean-Luc... - p. 147-155 , 2021

Link: https://dl.acm.org/doi/1..

8

Logical time control of concurrent DES:

Béchennec, Jean-Luc ; Lime, Didier ; Roux, Olivier H.
Discrete Event Dynamic Systems. 31 (2021) 2 - p. 185-217 , 2021

Link: https://doi.org/10.1007/..

9

Formal schedulability analysis based on multi-core RTOS mod..:

, In: 29th International Conference on Real-Time Networks and Systems,

Haur, Imane ; Béchennec, Jean-Luc ; Roux, Olivier Henri - p. 216-225 , 2021

Link: https://dl.acm.org/doi/1..

10

Requirement specification and model-checking of a real-time..:

, In: Proceedings of the 28th International Conference on Real-Time Networks and Systems,

Boukir, Khaoula ; Béchennec, Jean-Luc ; Déplanche, Anne-Marie - p. 89-99 , 2020

Link: https://dl.acm.org/doi/1..

11

Formal approach for a verified implementation of Global EDF..:

, In: Proceedings of the 26th International Conference on Real-Time Networks and Systems,

Boukir, Khaoula ; Béchennec, Jean-Luc ; Déplanche, Anne-Marie - p. 83-92 , 2018

Link: https://dl.acm.org/doi/1..

12

Formal Model-Based Synthesis of Application-Specific Static..:

Tigori, Kabland Toussaint Gautier ; Béchennec, Jean-Luc ; Faucou, Sébastien.
ACM Transactions on Embedded Computing Systems (TECS). 16 (2017) 4 - p. 1-25 , 2017

Link: https://dl.acm.org/doi/1..

13

Formal Model-Based Synthesis of Application-Specific Static..:

Tigori, Kabland Toussaint Gautier ; Béchennec, Jean-Luc ; Faucou, Sébastien.
ACM Transactions on Embedded Computing Systems. 16 (2017) 4 - p. 1-25 , 2017

Link: https://doi.org/10.1145/..

14

Formal Synthesis of Optimal RTOS:

, In: 2015 IEEE 17th International Conference on High Performance Computing and Communications, 2015 IEEE 7th International Symposium on Cyberspace Safety and Security, and 2015 IEEE 12th International Conference on Embedded Software and Systems,

Kabland, Toussaint Gautier Tigori ; Bechennec, Jean-Luc ; Roux, Olivier Henri - p. 977-983 , 2015

Link: https://doi.org/10.1109/..

15

STM-HRT : A Robust and Wait-Free STM for Hard Real-Time ..:

Cotard, Sylvain ; Queudet, Audrey ; Béchennec, Jean-Luc..
ACM Transactions on Embedded Computing Systems (TECS). 14 (2015) 4 - p. 1-25 , 2015

Link: https://dl.acm.org/doi/1..