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Baeck, Sangyeop
8  Ergebnisse:
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1

A 4.13-GHz UHS Pseudo Two-Port SRAM With BL Charge Time Red..:

Kim, Jeongkyun ; Yook, Byungho ; Lee, Youngo...
IEEE Journal of Solid-State Circuits.  59 (2024)  4 - p. 1216-1224 , 2024
Link: https://doi.org/10.1109/..
 
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2

A Static Contention-Free Dual-Edge-Triggered Flip-Flop with..:

, In: 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits),
Kim, Sekeon ; Cho, Keonhee ; Baek, Kyeongrim... - p. 1-2 , 2023
Link: https://doi.org/10.23919..
 
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3

A 4.0GHz UHS Pseudo Two-port SRAM with BL Charge Time Reduc..:

, In: 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits),
Kim, Jeongkyun ; Yook, Byungho ; Choi, Taemin... - p. 1-2 , 2023
Link: https://doi.org/10.23919..
 
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4

A 14-nm Low Voltage SRAM with Charge-Recycling and Charge S..:

, In: 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits),
Cho, Keonhee ; Kim, Giseok ; Oh, Jisang... - p. 214-215 , 2022
Link: https://doi.org/10.1109/..
 
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5

3nm Gate-All-Around (GAA) Design-Technology Co-Optimization..:

, In: 2022 IEEE Custom Integrated Circuits Conference (CICC),
Song, Taejoong ; Jung, Hakchul ; Yang, Giyoung... - p. 1-7 , 2022
Link: https://doi.org/10.1109/..
 
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6

4nm Voltage Auto-Tracking SRAM Pulse Generator with Fully R..:

, In: 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits),
Lee, Inhak ; Seo, Dongwook ; Li, Yunrong.. - p. 218-219 , 2022
Link: https://doi.org/10.1109/..
 
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7

5-nm Low-Power SRAM Featuring Dual-Rail Architecture With V..:

Baeck, Sangyeop ; Lee, Inhak ; Tang, Hoyoung...
IEEE Solid-State Circuits Letters.  5 (2022)  - p. 50-53 , 2022
Link: https://doi.org/10.1109/..
 
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8

5nm Low Power SRAM Featuring Dual-Rail Architecture with Vo..:

, In: 2021 Symposium on VLSI Circuits,
Baeck, Sangyeop ; Lee, Inhak ; Tang, Hoyoung... - p. 1-2 , 2021
Link: https://doi.org/10.23919..
 
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