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Banerjee, Sabyasachee
6  Ergebnisse:
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1

On Managing Test-Time, Power, and Layer Assignment in 3D So..:

, In: 2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID),
Banerjee, Sabyasachee ; Majumder, Subhashis ; Bhattacharya, Bhargab B. - p. 684-689 , 2024
Link: https://doi.org/10.1109/..
 
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2

Fast algorithms for test optimization of core based 3D SoC:

Banerjee, Sabyasachee ; Majumder, Subhashis ; Das, Debesh K..
Integration.  77 (2021)  - p. 70-88 , 2021
Link: https://doi.org/10.1016/..
 
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3

Designing balanced wrapper chains in 3D SoC under constrain..:

Banerjee, Sabyasachee ; Ghorui, Soumendu ; Majumder, Subhashis
Innovations in Systems and Software Engineering.  17 (2021)  3 - p. 219-230 , 2021
Link: https://doi.org/10.1007/..
 
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4

A TSV Constrained Algorithm for Designing Balanced Wrapper ..:

, In: Lecture Notes in Networks and Systems; Advanced Computing and Systems for Security: Volume 13,
Banerjee, Sabyasachee ; Ghorui, Soumendu ; Majumder, Subhashis - p. 35-47 , 2021
Link: https://doi.org/10.1007/..
 
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5

A Deterministic Multi-layered Partitioning Tool for Wire-Le..:

, In: 2019 IEEE 26th International Conference on High Performance Computing, Data, and Analytics (HiPC),
Ghorui, Soumendu ; Banerjee, Sabyasachee ; Majumder, Subhashis - p. 44-51 , 2019
Link: https://doi.org/10.1109/..
 
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6

Speed Optimization In Unplanned Traffic Using Bio-Inspired ..:

Ghosal, Prasun ; Chakraborty, Arijit ; Banerjee, Sabyasachee.
http://arxiv.org/abs/1212.2866.  , 2012
Link: http://arxiv.org/abs/121..
 
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