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Batude, P.
70  Ergebnisse:
Personensuche X
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1

Ultimate Layer Stacking Technology for High Density Sequent..:

, In: 2023 International Electron Devices Meeting (IEDM),
Radu, I. ; Nguyen, B-Y. ; Chang, C-H.... - p. 1-4 , 2023
Link: https://doi.org/10.1109/..
 
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2

3D sequential integration with Si CMOS stacked on 28nm indu..:

, In: 2023 International Electron Devices Meeting (IEDM),
Mota-Frutuoso, T. ; Lapras, V. ; Brunet, L.... - p. 1-4 , 2023
Link: https://doi.org/10.1109/..
 
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3

Extracting edge conduction around threshold in mesa-isolate..:

Boutayeb, A. ; Theodorou, C. ; Golanski, D....
Solid-State Electronics.  209 (2023)  - p. 108736 , 2023
Link: https://doi.org/10.1016/..
 
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4

3-Tier BSI CIS with 3D Sequential & Hybrid Bonding Enabling..:

, In: 2022 International Electron Devices Meeting (IEDM),
Guyader, F. ; Batude, P. ; Malinge, P.... - p. 37.4.1-37.4.4 , 2022
Link: https://doi.org/10.1109/..
 
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5

Methodology for Active Junction Profile Extraction in thin ..:

, In: 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits),
Frutuoso, T. Mota ; Garros, X. ; Batude, P.... - p. 332-333 , 2022
Link: https://doi.org/10.1109/..
 
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6

A Review of Low Temperature Process Modules Leading Up to t..:

Fenouillet-Beranger, C. ; Brunet, L. ; Batude, P....
IEEE Transactions on Electron Devices.  68 (2021)  7 - p. 3142-3148 , 2021
Link: https://doi.org/10.1109/..
 
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7

3D sequential integration: applications and associated key ..:

, In: 2021 IEEE International Electron Devices Meeting (IEDM),
Batude, P. ; Billoint, O. ; Thuries, S.... - p. 3.2.1-3.2.4 , 2021
Link: https://doi.org/10.1109/..
 
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8

28nm FDSOI CMOS technology (FEOL and BEOL) thermal stabilit..:

, In: 2020 IEEE Symposium on VLSI Technology,
Cavalcante, C. ; Fenouillet-Beranzer, C. ; Batude, P.... - p. 1-2 , 2020
Link: https://doi.org/10.1109/..
 
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9

Novel fine-grain back-bias assist techniques for 3D-monolit..:

Bosch, D. ; Garros, X. ; Makosiej, A....
Solid-State Electronics.  168 (2020)  - p. 107720 , 2020
Link: https://doi.org/10.1016/..
 
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10

Inter-tier electrostatic coupling effects in 3D sequential ..:

Sideris, P. ; Brunet, L. ; Ciampolini, L....
Solid-State Electronics.  168 (2020)  - p. 107715 , 2020
Link: https://doi.org/10.1016/..
 
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11

Comparative experimental study of junctionless and inversio..:

, In: 2020 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA),
Bosch, D. ; Colinge, J.P. ; Lugo, J.... - p. 126-127 , 2020
Link: https://doi.org/10.1109/..
 
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12

Low temperature high voltage analog devices in a 3D sequent..:

, In: 2020 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA),
Cavalcante, C. ; Garros, X. ; Batude, P.... - p. 155-156 , 2020
Link: https://doi.org/10.1109/..
 
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13

All-operation-regime characterization and modeling of drain..:

, In: 2020 IEEE Symposium on VLSI Technology,
Bosch, D. ; Colinge, J.P. ; Ghibaudo, G.... - p. 1-2 , 2020
Link: https://doi.org/10.1109/..
 
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14

First demonstration of low temperature $(\leq 500^{\circ}\m..:

, In: 2020 IEEE Symposium on VLSI Technology,
Fenouillet-Beranger, C. ; Brunet, L. ; Batude, P.... - p. 1-2 , 2020
Link: https://doi.org/10.1109/..
 
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15

Statistical Characterization and Modelling of Gate-Induced ..:

, In: 2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S),
Karatsori, T. A. ; Cavalcante, C. ; Lacord, J.... - p. 1-2 , 2019
Link: https://doi.org/10.1109/..
 
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