Bhuvanendran Nair Gourikutty, Sajay
25  Ergebnisse:
Personensuche X
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1

Solutions for Process Challenges on Fan-Out Wafer Level Pac..:

, In: 2023 IEEE 25th Electronics Packaging Technology Conference (EPTC),
 
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2

Defect Localization in Through-Si-Interposer Based 2.5D ICs:

, In: 2020 IEEE 70th Electronic Components and Technology Conference (ECTC),
 
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6

Direct-Drive 224 Gbps/λ PAM4 and 112 Gbps/λ NRZ Silicon Pho..:

, In: 2024 IEEE Silicon Photonics Conference (SiPhotonics),
 
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7

A Compact Wafer-Level Heterogeneously Integrated Scalable O..:

, In: 2024 IEEE 74th Electronic Components and Technology Conference (ECTC),
 
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8

Characterization of Differential TMV Vertical Interconnects..:

, In: 2023 IEEE 25th Electronics Packaging Technology Conference (EPTC),
 
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9

Physical Verification for 3D Heterogeneous Integrated Elect..:

, In: 2023 IEEE 25th Electronics Packaging Technology Conference (EPTC),
 
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10

A Heterogeneously Integrated Wafer-level Processed Co-Packa..:

, In: 2023 IEEE 73rd Electronic Components and Technology Conference (ECTC),
 
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11

Optimization of micro-fabricated porous membranes for intes..:

Sajay, Bhuvanendran Nair Gourikutty ; Yin, Chiam Su ; Ramadan, Qasem
Journal of Micromechanics and Microengineering.  27 (2017)  12 - p. 124004 , 2017
 
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