Chao, Mango C.-T.
55  Ergebnisse:
Personensuche X
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1

Test Generation for Defect-Based Faults of Scan Flip-Flops:

, In: 2023 IEEE 41st VLSI Test Symposium (VTS),
Nien, Yu-Teng ; Li, Chen-Hong ; Wu, Pei-Yin... - p. 1-7 , 2023
 
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2

Rule Generation for Classifying SLT Failed Parts:

, In: 2022 IEEE 40th VLSI Test Symposium (VTS),
Hsu, Ho-Chieh ; Lu, Cheng-Che ; Wang, Shih-Wei... - p. 1-7 , 2022
 
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3

Path-Based Pre-Routing Timing Prediction for Modern Very La..:

, In: 2022 23rd International Symposium on Quality Electronic Design (ISQED),
Chen, Li-Wei ; Sui, Yao-Nien ; Lee, Tai-Cheng... - p. 1-6 , 2022
 
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4

A Reinforcement Learning Agent for Obstacle-Avoiding Rectil..:

, In: Proceedings of the 2022 International Symposium on Physical Design,
Chen, Po-Yan ; Ke, Bing-Ting ; Lee, Tai-Cheng... - p. 107-115 , 2022
 
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5

Test Methodology for Defect-Based Bridge Faults:

Chang, Shuo-Wen ; Nien, Yu-Teng ; Hu, Yu-Pang...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  30 (2022)  7 - p. 975-988 , 2022
 
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6

Power distribution network generation for optimizing IR-dro..:

, In: Proceedings of the 39th International Conference on Computer-Aided Design,
 
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7

Test Methodology for Defect-based Bridge Faults:

, In: 2020 IEEE International Test Conference in Asia (ITC-Asia),
Hu, Yu-Pang ; Chang, Shuo-Wen ; Wu, Kai-Chiang... - p. 106-111 , 2020
 
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8

Predicting Shot-Level SRAM Read/Write Margin Based on Measu..:

Bin, Shu-Yung ; Lin, Shih-Feng ; Cheng, Ya-Ching...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  24 (2016)  2 - p. 625-637 , 2016
 
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9

Statistical methodology to identify optimal placement of on..:

, In: Proceedings of the 35th International Conference on Computer-Aided Design,
 
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10

Generating Routing-Driven Power Distribution Networks with ..:

, In: Proceedings of the 2016 on International Symposium on Physical Design,
Chang, Wen-Hsiang ; Chen, Li-De ; Lin, Chien-Hsueh... - p. 145-152 , 2016
 
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11

Statistical Framework and Built-In Self-Speed-Binning Syste..:

Mu, Szu-Pang ; Chao, Mango C.-T. ; Chen, Shi-Hao.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  24 (2016)  5 - p. 1675-1687 , 2016
 
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12

Practical Routability-Driven Design Flow for Multilayer Pow..:

Chang, Wen-Hsiang ; Chao, Mango C.-T ; Chen, Shi-Hao
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  22 (2014)  5 - p. 1069-1081 , 2014
 
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13

Novel Circuit-Level Model for Gate Oxide Short and its Test..:

Lin, Chen-Wei ; Chao, Mango C.-T. ; Hsu, Chih-Chieh
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  22 (2014)  6 - p. 1294-1307 , 2014
 
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14

Power-Up Sequence Control for MTCMOS Designs:

Chen, Shi-Hao ; Lin, Youn-Long ; Chao, Mango C.-T.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  21 (2013)  3 - p. 413-423 , 2013
 
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15

Alternate hammering test for application-specific DRAMs and..:

, In: Proceedings of the 49th Annual Design Automation Conference,
Huang, Rei-Fu ; Yang, Hao-Yu ; Chao, Mango C.-T.. - p. 1012-1017 , 2012
 
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