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Chhandak, Mukherjee
151  Ergebnisse:
Personensuche X
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1

Understanding the Substrate Effect on De-embedding Structur..:

, In: 2024 IEEE 36th International Conference on Microelectronic Test Structures (ICMTS),
Wesling, Bruno Neckel ; Deng, Marina ; Mukherjee, Chhandak... - p. 1-5 , 2024
Link: https://doi.org/10.1109/..
 
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2

Signature of electrothermal transport in 18nm vertical junc..:

Rezgui, Houssem ; Wang, Yifan ; Mukherjee, Chhandak..
Journal of Physics D: Applied Physics.  , 2024
Link: https://doi.org/10.1088/..
 
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3

High Efficiency O‐band Preamplified Receiver Integrated wit..:

Gnanamani, Risab ; Bertin, Hervé ; Besancon, Claire...
physica status solidi (a).  221 (2024)  13 - p. , 2024
Link: https://doi.org/10.1002/..
 
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4

3-D Logic Circuit Design-Oriented Electrothermal Modeling o..:

Mannaa, Sara ; Poittevin, Arnaud ; Marchand, Cédric...
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits.  9 (2023)  2 - p. 116-123 , 2023
Link: https://doi.org/10.1109/..
 
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5

Thermal consideration in nanoscale gate-all-around vertical..:

, In: 2023 Silicon Nanoelectronics Workshop (SNW),
Larrieu, Guilhem ; Rezgui, Houssem ; Kumar, Abhishek... - p. 27-28 , 2023
Link: https://doi.org/10.23919..
 
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6

(Invited) Strategies for Characterization and Parameter Ext..:

Maneux, Cristell ; Mukherjee, Chhandak ; Deng, Marina...
ECS Transactions.  111 (2023)  1 - p. 209-217 , 2023
Link: https://doi.org/10.1149/..
 
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7

InP DHBT Analytical Modeling: Toward THz Transistors:

Davy, Nil ; Nodjiadjim, Virginie ; Riet, Muriel...
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.  42 (2023)  11 - p. 4102-4111 , 2023
Link: https://doi.org/10.1109/..
 
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8

Electrothermal modeling of junctionless vertical Si nanowir..:

, In: ESSDERC 2023 - IEEE 53rd European Solid-State Device Research Conference (ESSDERC),
Wang, Yifan ; Mukherjee, Chhandak ; Rezgui, Houssem... - p. 57-60 , 2023
Link: https://doi.org/10.1109/..
 
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9

Analysis of an Inverter Logic Cell based on 3D Vertical Nan..:

, In: 2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC),
Reveil, Lucas ; Mukherjee, Chhandak ; Maneux, Cristell... - p. 1-2 , 2022
Link: https://doi.org/10.1109/..
 
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10

A Logic Cell Design and routing Methodology Specific to VNW..:

, In: 2022 20th IEEE Interregional NEWCAS Conference (NEWCAS),
Poittevin, Arnaud ; O'Connor, Ian ; Marchand, Cedric... - p. 460-464 , 2022
Link: https://doi.org/10.1109/..
 
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11

Extraction of small-signal equivalent circuit for de-embedd..:

Neckel Wesling, Bruno ; Deng, Marina ; Mukherjee, Chhandak...
Solid-State Electronics.  194 (2022)  - p. 108359 , 2022
Link: https://doi.org/10.1016/..
 
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12

InP DHBT test structure optimization towards 110 GHz charac..:

, In: ESSDERC 2022 - IEEE 52nd European Solid-State Device Research Conference (ESSDERC),
Davy, Nil ; Deng, Marina ; Nodjiadjim, Virginie... - p. 320-323 , 2022
Link: https://doi.org/10.1109/..
 
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13

Circuit Design Flow dedicated to 3D vertical nanowire FET:

, In: 2022 IEEE Latin American Electron Devices Conference (LAEDC),
Maneux, Cristell ; Mukherjee, Chhandak ; Deng, Marina... - p. 1-4 , 2022
Link: https://doi.org/10.1109/..
 
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14

Performance prediction of InP/GaAsSb double heterojunction ..:

Wen, Xin ; Arabhavi, Akshay ; Quan, Wei...
Journal of Applied Physics.  130 (2021)  3 - p. , 2021
Link: https://doi.org/10.1063/..
 
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15

3D Logic Cells Design and Results Based on Vertical NWFET T..:

, In: VLSI-SoC: Design Trends; IFIP Advances in Information and Communication Technology,
Poittevin, Arnaud ; Mukherjee, Chhandak ; O'Connor, Ian... - p. 301-321 , 2021
Link: https://doi.org/10.1007/..
 
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