E-LIB Suche - Ergebnisse für: Cristal Kestelman, Adrián

1

An Experimental Study of Reduced-Voltage Operation in Moder..:

, In: 2020 50th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN),

Salami, Behzad ; Onural, Erhan Baturay ; Yuksel, Ismail Emir... - p. 138-149 , 2020

2

MoRS: An Approximate Fault Modeling Framework for Reduced-V..:

Yuksel, Ismail Emir ; Salami, Behzad ; Ergin, Oguz..
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 41 (2022) 6 - p. 1663-1673 , 2022

Link: https://doi.org/10.1109/..

3

Can We Trust Undervolting in FPGA-Based Deep Learning Desig..:

Koc, Fahrettin ; Salami, Behzad ; Ergin, Oguz..
IEEE Micro. 42 (2022) 3 - p. 57-65 , 2022

Link: https://doi.org/10.1109/..

4

Comprehensive evaluation of supply voltage underscaling in ..:

, In: Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture,

Salami, Behzad ; Unsal, Osman S. ; Kestelman, Adrian Cristal - p. 724-736 , 2018

Link: https://dl.acm.org/doi/1..

5

Mth: Codesigned Hardware/Software Support for Fine Grain Th..:

Marquez, David Gonzalez ; Kestelman, Adrian Cristal ; Mocskos, Esteban
IEEE Computer Architecture Letters. 16 (2017) 1 - p. 64-67 , 2017

Link: https://doi.org/10.1109/..

6

System-level power estimation tool for embedded processor b..:

, In: Proceedings of the 6th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools,

Rethinagiri, Santhosh Kumar ; Palomar, Oscar ; Ben Atitallah, Rabie... - p. 1-8 , 2014

Link: https://dl.acm.org/doi/1..

7

Vitruvius+: An area-efficient RISC-V decoupled vector copro..:

Minervini Minervini, Francesco ; Palomar Pérez, Óscar ; Unsal, Osman Sabri...
https://dl.acm.org/doi/full/10.1145/3575861. , 2023

Link: http://hdl.handle.net/21..

8

Mix-GEMM: An efficient HW-SW architecture for mixed-precisi..:

Reggiani, Enrico ; Pappalardo, Alessandro ; Doblas Font, Max...
https://ieeexplore.ieee.org/document/10071076. , 2023

Link: http://hdl.handle.net/21..

9

DVINO: A RISC-V vector processor implemented in 65nm techno..:

Cabo Pitarch, Guillem ; Candon, Gerard ; Carril, Xavier...
https://ieeexplore.ieee.org/document/9970128. , 2022

Link: http://hdl.handle.net/21..

10

BiSon-e: a lightweight and high-performance accelerator for..:

Reggiani, Enrico ; Ramírez Lazo, Cristóbal ; Figueras Bagué, Roger...
https://dl.acm.org/doi/10.1145/3503222.3507746. , 2022

Link: http://hdl.handle.net/21..

11

MoRS: An approximate fault modelling framework for reduced-..:

Yuksel, Ismail Emir ; Salami, Behzad ; Ergin, Oguz..
https://ieeexplore.ieee.org/document/9570819/. , 2022

Link: http://hdl.handle.net/21..

12

Adaptable register file organization for vector processors:

Ramírez Lazo, Cristóbal ; Reggiani, Enrico ; Rojas Morales, Carlos...
https://ieeexplore.ieee.org/document/9773222. , 2022

Link: http://hdl.handle.net/21..

13

Can we trust undervolting in FPGA-based deep learning desig..:

Koc, Fahrettin ; Salami, Behzad ; Ergin, Oguz..
https://ieeexplore.ieee.org/document/9721609. , 2022

Link: http://hdl.handle.net/21..

14

Towards zero-waste recovery and zero-overhead checkpointing..:

Keller, Kai Rasmus ; Cristal Kestelman, Adrián ; Bautista Gomez, Leonardo
https://ieeexplore.ieee.org/document/9680377. , 2021

Link: http://hdl.handle.net/21..

15

VIA: A smart scratchpad for vector units with application t..:

Pavón Rivera, Julián ; Vargas Valdivieso, Iván ; Barredo Ferreira, Adrián...
https://ieeexplore.ieee.org/document/9407226. , 2021

Link: http://hdl.handle.net/21..