Datta, Debarshi
44  Ergebnisse:
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1

Hardware optimized digital down converter for multi-standar..:

Datta, Debarshi ; Dutta, Himadri Sekhar
Analog Integrated Circuits and Signal Processing.  118 (2024)  3 - p. 567-575 , 2024
 
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Hardware efficient reconfigurable digital down converter fo..:

Datta, Debarshi ; Dutta, Himadri Sekhar
International Journal of Electronics Letters.  12 (2023)  2 - p. 107-118 , 2023
 
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High Efficient Half-Band Decimation Filter on FPGA:

Datta, Debarshi ; Dutta, Himadri Sekhar
Transactions of the Indian National Academy of Engineering.  8 (2023)  2 - p. 317-323 , 2023
 
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Area and power-efficient reconfigurable digital down conver..:

Datta, Debarshi ; Dutta Sekhar, Himadri
Facta universitatis - series: Electronics and Energetics.  35 (2022)  2 - p. 243-252 , 2022
 
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Predicting the Severity of COVID-19 Respiratory Illness wit..:

Shorten, Connor ; Khoshgoftaar, Taghi M. ; Hashemi, Javad...
The International FLAIRS Conference Proceedings.  35 (2022)  - p. , 2022
 
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10

CIC Decimation Filter Implementation on FPGA:

Datta, Debarshi ; Dutta, Himadri Sekhar
Journal of The Institution of Engineers (India): Series B.  104 (2022)  1 - p. 85-90 , 2022
 
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Paper title: a highly efficient implementation of fractiona..:

Datta, Debarshi ; Dutta, Himadri Sekhar
International Journal of Information Technology.  15 (2022)  1 - p. 101-106 , 2022
 
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12

Exploring Language-Interfaced Fine-Tuning for COVID-19 Pati..:

, In: 2022 IEEE 34th International Conference on Tools with Artificial Intelligence (ICTAI),
 
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High performance IIR filter implementation on FPGA:

Datta, Debarshi ; Dutta, Himadri Sekhar
Journal of Electrical Systems and Information Technology.  8 (2021)  1 - p. , 2021
 
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High Efficient Polyphase Digital Down Converter on FPGA:

Datta, Debarshi ; Dutta, Himadri Sekhar
Circuits, Systems, and Signal Processing.  40 (2021)  11 - p. 5787-5798 , 2021
 
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FPGA Implementation of Symmetric Systolic FIR Filter using ..:

, In: 2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS),
 
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