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2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) ,
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Scaled FinFETs Connected by Using Both Wafer Sides for Rout..:
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2021 IEEE International Electron Devices Meeting (IEDM) ,
2
Buried Power Rail Metal exploration towards the 1 nm Node:
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2020 IEEE Symposium on VLSI Technology ,
3
Buried Power Rail Integration with Si FinFETs for CMOS Scal..:
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2020 IEEE Silicon Nanoelectronics Workshop (SNW) ,
4
Scaled transistors with 2D materials from the 300mm fab:
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2020 IEEE Symposium on VLSI Technology ,
5
First Monolithic Integration of 3D Complementary FET (CFET)..:
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2020 IEEE International Electron Devices Meeting (IEDM) ,
6
Buried Power Rail Scaling and Metal Assessment for the 3 nm..:
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2020 IEEE Symposium on VLSI Technology ,
7
3D sequential low temperature top tier devices using dopant..:
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2019 IEEE International Electron Devices Meeting (IEDM) ,
8
Vertical Nanowire and Nanosheet FETs: Device Features, Nove..:
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2017 IEEE International Memory Workshop (IMW) ,
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