Farcy, Alexis
72  Ergebnisse:
Personensuche X
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1

2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked ..:

, In: 2020 IEEE International Solid- State Circuits Conference - (ISSCC),
 
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Co-integration of TSV mid process and optical devices for S..:

, In: 2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC),
 
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3

Preface:

Thomas, Olivier ; Farcy, Alexis ; Maitrejean, Sylvain.
Microelectronic Engineering.  156 (2016)  - p. 1 , 2016
 
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Preface:

Chenevier, Bernard ; Farcy, Alexis ; Maîtrejean, Sylvain
Microelectronic Engineering.  87 (2010)  3 - p. 243-244 , 2010
 
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Backside cavities for thermal tuning optimization of silico..:

Tissier, Pierre ; Hassan, Karim ; Reboud, Vincent...
info:eu-repo/semantics/altIdentifier/doi/10.1109/ECTC32696.2021.00264.  , 2021
 
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11

Backside cavities for thermal tuning optimization of silico..:

Tissier, Pierre ; Hassan, Karim ; Reboud, Vincent...
info:eu-repo/semantics/altIdentifier/doi/10.1109/ECTC32696.2021.00264.  , 2021
 
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12

IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on..:

Vivet, Pascal ; Guthmuller, Eric ; Thonnart, Yvain...
info:eu-repo/semantics/altIdentifier/doi/10.1109/JSSC.2020.3036341.  , 2021
 
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13

IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on..:

Vivet, Pascal ; Guthmuller, Eric ; Thonnart, Yvain...
info:eu-repo/semantics/altIdentifier/doi/10.1109/JSSC.2020.3036341.  , 2021
 
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14

Backside cavities for thermal tuning optimization of silico..:

Tissier, Pierre ; Hassan, Karim ; Reboud, Vincent...
info:eu-repo/semantics/altIdentifier/doi/10.1109/ECTC32696.2021.00264.  , 2021
 
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15

Backside cavities for thermal tuning optimization of silico..:

Tissier, Pierre ; Hassan, Karim ; Reboud, Vincent...
info:eu-repo/semantics/altIdentifier/doi/10.1109/ECTC32696.2021.00264.  , 2021
 
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