Fujiwara, Hidehiro
76  Ergebnisse:
Personensuche X
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1

34.4 A 3nm, 32.5TOPS/W, 55.0TOPS/mm2 and 3.78Mb/mm2 Fully-D..:

, In: 2024 IEEE International Solid-State Circuits Conference (ISSCC),
Fujiwara, Hidehiro ; Mori, Haruki ; Zhao, Wei-Chang... - p. 572-574 , 2024
 
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Efficient Processing of MLPerf Mobile Workloads Using Digit..:

Sun, Xiaoyu ; Cao, Weidong ; Crafton, Brian...
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.  43 (2024)  4 - p. 1191-1205 , 2024
 
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A 3nm Fin-FET 19.87-Mbit/mm2 2RW Pseudo Dual-Port 6T SRAM w..:

, In: 2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits),
 
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20.1 NVE: A 3nm 23.2TOPS/W 12b-Digital-CIM-Based Neural Eng..:

, In: 2024 IEEE International Solid-State Circuits Conference (ISSCC),
Shih, Ming-En ; Hsieh, Shih-Wei ; Tsai, Ping-Yuan... - p. 360-362 , 2024
 
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High-Speed Embedded Memory for AI and High-Performance Comp..:

, In: 2023 International Electron Devices Meeting (IEDM),
Wang, Yih ; Chen, Yen-Huei ; Chih, Y.D.... - p. 1-4 , 2023
 
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3.7-GHz Multi-Bank High-Current Single-Port Cache SRAM with..:

, In: 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits),
 
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A 4nm 6163-TOPS/W/b $\mathbf{4790-TOPS/mm^{2}/b}$ SRAM Base..:

, In: 2023 IEEE International Solid- State Circuits Conference (ISSCC),
Mori, Haruki ; Zhao, Wei-Chang ; Lee, Cheng-En... - p. 132-134 , 2023
 
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A 3nm 256Mb SRAM in FinFET Technology with New Array Bankin..:

, In: 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits),
Chang, Jonathan ; Chen, Yen-Huei ; Chan, Gary... - p. 1-2 , 2023
 
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A 12nm 121-TOPS/W 41.6-TOPS/mm2 All Digital Full Precision ..:

, In: 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits),
Lee, Chia-Fu ; Lu, Cheng-Han ; Lee, Cheng-En... - p. 24-25 , 2022
 
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A 5-nm 254-TOPS/W 221-TOPS/mm2 Fully-Digital Computing-in-M..:

, In: 2022 IEEE International Solid- State Circuits Conference (ISSCC),
 
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15.1 A 5nm 135Mb SRAM in EUV and High-Mobility-Channel FinF..:

, In: 2020 IEEE International Solid- State Circuits Conference - (ISSCC),
Chang, Jonathan ; Chen, Yen-Huei ; Chan, Gary... - p. 238-240 , 2020
 
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A 28-nm 1R1W Two-Port 8T SRAM Macro With Screening Circuitr..:

Yabuuchi, Makoto ; Tsukamoto, Yasumasa ; Fujiwara, Hidehiro...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  26 (2018)  11 - p. 2335-2344 , 2018
 
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A 40-nm Resilient Cache Memory for Dynamic Variation Tolera..:

NAKATA, Yohei ; KIMI, Yuta ; OKUMURA, Shunsuke...
IEICE Transactions on Electronics.  E97.C (2014)  4 - p. 332-341 , 2014
 
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Divided Static Random Access Memory for Data Aggregation in..:

MATSUDA, Takashi ; IZUMI, Shintaro ; SAKAI, Yasuharu...
IEICE Transactions on Communications.  E95-B (2012)  1 - p. 178-188 , 2012
 
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