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Girard, Patrick
2058  Ergebnisse:
Personensuche X
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1

IDLD: Interlocked Dual-Circle Latch Design with Low Cost an..:

, In: Proceedings of the Great Lakes Symposium on VLSI 2024,
Yan, Aibin ; Dong, Chen ; Guo, Xing... - p. 19-24 , 2024
Link: https://dl.acm.org/doi/1..
 
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2

Nonvolatile and SEU-Recoverable Latch Based on FeFET and CM..:

, In: 2024 IEEE International Symposium on Circuits and Systems (ISCAS),
Yan, Aibin ; Lin, Zhuoyuan ; Liu, Guangzhu... - p. 1-5 , 2024
Link: https://doi.org/10.1109/..
 
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3

Resource constraint scheduling on two dedicated machines: A..:

Mesli-Kesraoui, Ouissem ; Ledreck, Loic ; Grolleau, Emmanuel...
EURO Journal on Computational Optimization.  12 (2024)  - p. 100093 , 2024
Link: https://doi.org/10.1016/..
 
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4

FeMPIM: A FeFET-Based Multifunctional Processing-in-Memory ..:

Yan, Aibin ; Chen, Yu ; Gao, Zhongyu...
IEEE Transactions on Circuits and Systems II: Express Briefs.  71 (2024)  4 - p. 2299-2303 , 2024
Link: https://doi.org/10.1109/..
 
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5

MURLAV: A Multiple-Node-Upset Recovery Latch and Algorithm-..:

Yan, Aibin ; Li, Zhixing ; Gao, Zhongyu...
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.  43 (2024)  7 - p. 2205-2214 , 2024
Link: https://doi.org/10.1109/..
 
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6

Nonvolatile Latch Designs With Node-Upset Tolerance and Rec..:

Yan, Aibin ; Wang, Litao ; Cui, Jie...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  32 (2024)  1 - p. 116-127 , 2024
Link: https://doi.org/10.1109/..
 
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7

Designs of BCD Adder Based on Excess-3 Code in Quantum-Dot ..:

Yan, Aibin ; Liu, Runqi ; Cui, Jie...
IEEE Transactions on Circuits and Systems II: Express Briefs.  70 (2023)  6 - p. 2256-2260 , 2023
Link: https://doi.org/10.1109/..
 
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8

High Performance and DNU-Recovery Spintronic Retention Latc..:

, In: 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE),
Yan, Aibin ; Zhou, Zhen ; Ding, Liang... - p. 1-2 , 2023
Link: https://doi.org/10.23919..
 
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9

Learning-Based Characterization Models for Quality Assuranc..:

, In: 2023 IEEE European Test Symposium (ETS),
Xhafa, Xhesila ; Girard, Patrick ; Virazel, Arnaud - p. 1-2 , 2023
Link: https://doi.org/10.1109/..
 
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10

A Low Area and Low Delay Latch Design with Complete Double-..:

, In: Proceedings of the Great Lakes Symposium on VLSI 2023,
Yan, Aibin ; Wei, Shaojie ; Zhang, Jinjun... - p. 167-171 , 2023
Link: https://dl.acm.org/doi/1..
 
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11

Designs of Array Multipliers with an Optimized Delay in Qua..:

Yan, Aibin ; Li, Xuehua ; Liu, Runqi...
Electronics.  12 (2023)  14 - p. 3189 , 2023
Link: https://doi.org/10.3390/..
 
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12

Designs of Two Quadruple-Node-Upset Self-Recoverable Latche..:

Yan, Aibin ; Li, Zhixing ; Cui, Jie...
IEEE Transactions on Aerospace and Electronic Systems.  59 (2023)  3 - p. 2885-2897 , 2023
Link: https://doi.org/10.1109/..
 
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13

A Low Overhead and Double-Node-Upset Self-Recoverable Latch:

, In: 2023 IEEE International Test Conference in Asia (ITC-Asia),
Yan, Aibin ; Xia, Fan ; Ni, Tianming... - p. 1-5 , 2023
Link: https://doi.org/10.1109/..
 
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14

Cell-Aware Model Generation Using Machine Learning:

, In: Frontiers of Quality Electronic Design (QED),
d'Hondt, Pierre ; Ladhar, Aymen ; Girard, Patrick. - p. 227-257 , 2023
Link: https://doi.org/10.1007/..
 
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15

Design of a Novel Latch with Quadruple-Node-Upset Recovery ..:

, In: 2023 IEEE International Test Conference in Asia (ITC-Asia),
Yan, Aibin ; Zhou, Chao ; Wei, Shaojie... - p. 1-6 , 2023
Link: https://doi.org/10.1109/..
 
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