E-LIB Suche - Ergebnisse für: Hartenstein, Reiner W.

1

Modeling and prototyping dynamically reconfigurable systems..:

, In: Proceedings of the 17th symposium on Integrated circuits and system design,

Ayala-Rincón, Mauricio ; Jacobi, Ricardo P. ; Carvalho, Luis G. A... - p. 248-253 , 2004

Link: https://dl.acm.org/doi/1..

2

Modeling a Reconfigurable System for Computing the FFT in P..:

, In: Proceedings of the 16th symposium on Integrated circuits and systems design,

Ayala-Rincón, Mauricio ; Nogueira, Rodrigo B. ; Llanos, Carlos H... - p. 205 ff. , 2003

Link: https://dl.acm.org/doi/1..

3

Applying ELAN Strategies in Simulating Processors over Simp..:

Ayala-Rincón, Mauricio ; Neto, Rinaldi Maya ; Jacobi, Ricardo P...
Electronic Notes in Theoretical Computer Science. 70 (2002) 6 - p. 84-99 , 2002

Link: https://doi.org/10.1016/..

4

Field-Programmable Logic and Applications From FPGAs to Com..

8th International Workshop, FPL '98 Tallinn, Estonia, Augus... Lecture Notes in Computer Science ; 1482

Hartenstein, Reiner W. ; Keevallik, Andres , 1998

Link: https://doi.org/10.1007/..

5

Performance Analysis in CoDe-X Partitioning for Structural ..:

, In: Proceedings of the 5th International Workshop on Hardware/Software Co-Design,

Hartenstein, Reiner W. ; Becker, Juergen - p. 141 ff. , 1997

Link: https://dl.acm.org/doi/1..

6

Field-programmable logic

smart applications, new paradigms and compilers ; 6th Inter... Lecture notes in computer science ; 1142

Hartenstein, Reiner W. , 1996

Link: http://dx.doi.org/10.100..

7

Null Bock auf High-Tech

Arbeitsplatzexport - nur weil die Löhne zu hoch sind? IT-Press-Sachbuch ; 06

Hartenstein, Reiner W. - Orig.-Ausg., 1. Aufl . , 1996

Exemplar: Zentrale:E02 a swl 790.7 2an/584

8

Two-level Partitioning of Image Processing Algorithms for t..:

, In: Proceedings of the 4th International Workshop on Hardware/Software Co-Design,

Hartenstein, Reiner W. ; Becker, Juergen ; Kress, Rainer - p. 77 ff. , 1996

Link: https://dl.acm.org/doi/1..

9

A datapath synthesis system for the reconfigurable datapath..:

, In: Proceedings of the 1995 Asia and South Pacific Design Automation Conference,

Hartenstein, Reiner W. ; Kress, Rainer - p. 77-es , 1995

Link: https://dl.acm.org/doi/1..

10

Combining structural and procedural programming by parallel..:

, In: Proceedings of the 1995 ACM symposium on Applied computing,

Hartenstein, Reiner W. ; Schmidt, Karin - p. 130-134 , 1995

Link: https://dl.acm.org/doi/1..

11

Wozu noch Mikro-Chips?

Einführung in Methoden der technischen Informatik ; zur An... IT-Press-Informat(ionstechn)ik, Serie technische Informatik ; 100

Hartenstein, Reiner W. - Orig.-Ausg., 1. Aufl . , 1994

Exemplar: Zentrale:Magazin tb 2598

12

Field-programmable logic

architectures, synthesis and applications ; 4th Internation... Lecture notes in computer science ; 849

Hartenstein, Reiner W. , 1994

Link: http://dx.doi.org/10.100..

Exemplar: Zentrale:Magazin 01.P.5613

13

Synthesis of systolic architectures using the SYS3 system:

Hartenstein, Reiner W. ; Lemmert, Karin ; Riedmüller, Michael
Microprocessing and Microprogramming. 27 (1989) 1-5 - p. 479-486 , 1989

Link: https://doi.org/10.1016/..

14

Explicit fault modeling and hierarchical test pattern gener..:

Alfs, Gerold ; Hartenstein, Reiner W. ; Wodtko, Andrea
Microprocessing and Microprogramming. 27 (1989) 1-5 - p. 675-680 , 1989

Link: https://doi.org/10.1016/..

15

MLED: A multiple abstraction level graphical editor:

Hartenstein, Reiner W ; Welters, Udo
Microprocessing and Microprogramming. 21 (1987) 1-5 - p. 585-590 , 1987

Link: https://doi.org/10.1016/..