E-LIB Suche - Ergebnisse für: Hatefinasab, Seyedehsomayeh

1

Rule-Based Design for Low-Cost Double-Node Upset Tolerant S..:

Hatefinasab, Seyedehsomayeh ; Medina-Garcia, Alfredo ; Morales, Diego P...
IEEE Access. 11 (2023) - p. 1732-1741 , 2023

Link: https://doi.org/10.1109/..

2

Highly Reliable Quadruple-Node Upset-Tolerant D-Latch:

Hatefinasab, Seyedehsomayeh ; Ohata, Akiko ; Salinas, Alfonso..
IEEE Access. 10 (2022) - p. 31836-31850 , 2022

Link: https://doi.org/10.1109/..

3

Low-Cost Soft Error Robust Hardened D-Latch for CMOS Techno..:

Hatefinasab, Seyedehsomayeh ; Rodriguez, Noel ; García, Antonio.
Electronics. 10 (2021) 11 - p. 1256 , 2021

Link: https://doi.org/10.3390/..

4

Low-cost soft-error hardened D-Latch in nano CMOS technolog:

Hatefinasab, Seyedehsomayeh
Hatefinasab, Seyedehsomayeh. Low-cost soft-error hardened D-Latch in nano CMOS technology. Granada: Universidad de Granada, 2023. [https://hdl.handle.net/10481/89398]. , 2024

Link: https://hdl.handle.net/1..

5

Rule-Based Design for Low-Cost Double-Node Upset Tolerant S..:

Hatefinasab, Seyedehsomayeh ; Morales Santos, Diego Pedro ; Castillo Morales, María Encarnación.
S. Hatefinasab. [et al.]. "Rule-Based Design for Low-Cost Double-Node Upset Tolerant Self-Recoverable D-Latch," in IEEE Access, vol. 11, pp. 1732-1741, 2023, doi: [10.1109/ACCESS.2022.3233812]. , 2023

Link: https://hdl.handle.net/1..

6

Highly Reliable Quadruple-Node Upset-Tolerant D-Latch:

Hatefinasab, Seyedehsomayeh ; Salinas Castillo, Alfonso ; Castillo Morales, María Encarnación.
S. Hatefinasab. [et al.]. "Highly Reliable Quadruple-Node Upset-Tolerant D-Latch," in IEEE Access, vol. 10, pp. 31836-31850, 2022, doi: [10.1109/ACCESS.2022.3160448]. , 2022

Link: http://hdl.handle.net/10..

7

Low-Cost Soft Error Robust Hardened D-Latch for CMOS Techno..:

Hatefinasab, Seyedehsomayeh ; Rodríguez Santiago, Noel ; García Ríos, Antonio.
Hatefinasab, S.; Rodriguez, N.; García, A.; Castillo, E. Low-Cost Soft Error Robust Hardened D-Latch for CMOS Technology Circuit. Electronics 2021, 10, 1256. https:// doi.org/10.3390/electronics10111256. , 2021

Link: http://hdl.handle.net/10..

8

Rule-Based Design for Low-Cost Double-Node Upset Tolerant S..:

Seyedehsomayeh Hatefinasab ; Alfredo Medina-Garcia ; Diego P. Morales..
https://ieeexplore.ieee.org/document/10005109/. , 2023

Link: https://doi.org/10.1109/..

9

Highly Reliable Quadruple-Node Upset-Tolerant D-Latch:

Seyedehsomayeh Hatefinasab ; Akiko Ohata ; Alfonso Salinas..
https://ieeexplore.ieee.org/document/9737482/. , 2022

Link: https://doi.org/10.1109/..

10

Low-Cost Soft Error Robust Hardened D-Latch for CMOS Techno..:

Seyedehsomayeh Hatefinasab ; Noel Rodriguez ; Antonio García.
Microelectronics. , 2021

Link: https://doi.org/10.3390/..

11

Low-Cost Soft Error Robust Hardened D-Latch for CMOS Techno..:

Seyedehsomayeh Hatefinasab ; Noel Rodriguez ; Antonio García.
https://www.mdpi.com/2079-9292/10/11/1256. , 2021

Link: https://doi.org/10.3390/..