Hellings, Geert
73  Ergebnisse:
Personensuche X
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1

Impact of Sub-μm Wafer Thinning on Latch-Up Risk in DTCO/ST..:

Serbulova, Kateryna ; Chen, Shih-Hung ; Hellings, Geert...
IEEE Transactions on Electron Devices.  71 (2024)  4 - p. 2278-2283 , 2024
 
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3

Multi-VT Options at Scaled Vertical Pitch in Gate-All-Aroun..:

, In: 2024 8th IEEE Electron Devices Technology & Manufacturing Conference (EDTM),
 
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5

Compact Modeling and Design Exploration of Non-Destructive ..:

Xiang, Yang ; Mukherjee, Shankha ; Hellings, Geert...
IEEE Transactions on Electron Devices.  71 (2024)  8 - p. 4685-4691 , 2024
 
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6

DTCO of Nanosheet and Forksheet Architectures: Exploring Di..:

, In: 2024 8th IEEE Electron Devices Technology & Manufacturing Conference (EDTM),
 
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8

Physics-Based and Closed-Form Model for Cryo-CMOS Subthresh..:

Beckers, Arnout ; Michl, Jakob ; Grill, Alexander...
IEEE Transactions on Nanotechnology.  22 (2023)  - p. 590-596 , 2023
 
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9

CFET SRAM With Double-Sided Interconnect Design and DTCO Be..:

Liu, Hsiao-Hsuan ; Schuddinck, Pieter ; Pei, Zhenlin...
IEEE Transactions on Electron Devices.  70 (2023)  10 - p. 5099-5106 , 2023
 
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10

3D SRAM Macro Design in 3D Nanofabric Process Technology:

Abdi, Dawit Burusie ; Salahuddin, Shairfe M. ; Boemmels, Juergen...
IEEE Transactions on Circuits and Systems I: Regular Papers.  70 (2023)  7 - p. 2858-2867 , 2023
 
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11

Investigating Nanowire, Nanosheet and Forksheet FET Hot-Car..:

, In: 2023 IEEE International Reliability Physics Symposium (IRPS),
Vandemaele, Michiel ; Kaczer, Ben ; Bury, Erik... - p. 1-10 , 2023
 
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12

CFET SRAM DTCO, Interconnect Guideline, and Benchmark for C..:

Liu, Hsiao-Hsuan ; Salahuddin, Shairfe M. ; Chan, Boon Teik...
IEEE Transactions on Electron Devices.  70 (2023)  3 - p. 883-890 , 2023
 
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13

Co-integration Process Compatible Input/Output (I/O) Device..:

, In: ESSDERC 2022 - IEEE 52nd European Solid-State Device Research Conference (ESSDERC),
 
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14

ESD nMOSFETs in Advanced Bulk FinFET Technology With Dual S..:

Chen, Wen-Chieh ; Chen, Shih-Hung ; Chiarella, Thomas...
IEEE Transactions on Electron Devices.  69 (2022)  9 - p. 5357-5362 , 2022
 
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15

A Holistic Evaluation of Buried Power Rails and Back-Side P..:

Nibhanupudi, S. S. Teja ; Prasad, Divya ; Das, Shidhartha...
IEEE Transactions on Electron Devices.  69 (2022)  8 - p. 4453-4459 , 2022
 
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