Ich stimme zu, dass diese Seite Cookies verwende. Weitere Informationen finden Sie unter unseren Datenschutzerklärungen .
X
Hernández Luz, Carles
379  Ergebnisse:
Personensuche X
?
1

The RECIPE approach to challenges in deeply heterogeneous h..:

Agosta, Giovanni ; Fornaciari, William ; Atienza, David...
Microprocessors and Microsystems.  77 (2020)  - p. 103185 , 2020
Link: https://doi.org/10.1016/..
 
?
2

Challenges in Deeply Heterogeneous High Performance Systems:

, In: 2019 22nd Euromicro Conference on Digital System Design (DSD),
Agosta, Giovanni ; Tornero Gavila, Rafael ; Zapater Sancho, Marina... - p. 428-435 , 2019
Link: https://doi.org/10.1109/..
 
?
3

BAFFI: a bit-accurate fault injector for improved dependabi..:

Tuzov, Ilya ; de-Andrés-Martínez, David ; Ruiz, Juan Carlos.
2023 Design, Automation & Test in Europe Conference & Exhibition (DATE).  , 2023
Link: http://hdl.handle.net/10..
 
?
4

Accurately measuring contention in Mesh NoCs in time-sensit..:

Cardona Nadal, Jordi ; Hernández Luz, Carles ; Abella Ferrer, Jaume..
https://dl.acm.org/doi/abs/10.1145/3582006.  , 2023
Link: http://hdl.handle.net/21..
 
?
5

DVINO: A RISC-V vector processor implemented in 65nm techno..:

Cabo Pitarch, Guillem ; Candon, Gerard ; Carril, Xavier...
https://ieeexplore.ieee.org/document/9970128.  , 2022
Link: http://hdl.handle.net/21..
 
?
6

End-to-end QoS for the open source safety-relevant RISC-V S..:

Andreu Cerezo, Pablo ; Hernández Luz, Carles ; Picornell Sanjuan, Tomás...
https://arxiv.org/abs/2210.04683.  , 2022
Link: http://hdl.handle.net/21..
 
?
7

Achieving diverse redundancy for GPU Kernels:

Alcaide Portet, Sergi ; Kosmidis, Leonidas ; Hernández Luz, Carles.
https://ieeexplore.ieee.org/document/9523531.  , 2022
Link: http://hdl.handle.net/21..
 
?
8

SafeSU-2: a safe statistics unit for space MPSoCs:

Cabo Pitarch, Guillem ; Alcaide Portet, Sergi ; Hernández Luz, Carles...
https://ieeexplore.ieee.org/document/9774515.  , 2022
Link: http://hdl.handle.net/21..
 
?
9

A security model for randomization-based protected caches:

Ribes González, Jordi ; Farràs Ventura, Oriol ; Hernández Luz, Carles..
https://tches.iacr.org/index.php/TCHES/article/view/9693.  , 2022
Link: http://hdl.handle.net/21..
 
?
10

Improving the Robustness of Redundant Execution with Regist..:

Tuzov, Ilya ; Andreu, Pablo ; Medina, Laura...
2021 IEEE/ACM International Conference On Computer-Aided Design (ICCAD).  , 2021
Link: http://hdl.handle.net/10..
 
?
11

SafeSU: an extended statistics unit for multicore timing in..:

Cabo Pitarch, Guillem ; Bas Jalón, Francisco ; Lorenzo Ortega, Rubén...
https://ieeexplore.ieee.org/document/9465444.  , 2021
Link: http://hdl.handle.net/21..
 
?
12

Security, reliability and test aspects of the RISC-V ecosys..:

Abella Ferrer, Jaume ; Alcaide Portet, Sergi ; Anders, Jens...
https://ieeexplore.ieee.org/document/9465449.  , 2021
Link: http://hdl.handle.net/21..
 
?
13

Worst-Case Energy Consumption: A New Challenge for Battery-..:

Trilla, David ; Hernández Luz, Carles ; Abella, Jaume.
IEEE Transactions on Sustainable Computing.  , 2021
Link: http://hdl.handle.net/10..
 
?
14

Worst-case energy consumption: A new challenge for battery-..:

Trilla Rodríguez, David ; Hernández Luz, Carles ; Abella Ferrer, Jaume.
https://ieeexplore.ieee.org/document/8847394.  , 2021
Link: http://hdl.handle.net/21..
 
?
15

Enforcing Predictability of Many-cores with DCFNoC:

Picornell-Sanjuan, Tomás ; Flich Cardo, José ; Hernández Luz, Carles.
IEEE Transactions on Computers.  , 2021
Link: http://hdl.handle.net/10..
 
1-15