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Hikavyy, A. Y.
15  Ergebnisse:
Personensuche X
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1

Processing Technologies for Advanced Ge Devices:

Loo, R. ; Hikavyy, A. Y. ; Witters, L....
ECS Journal of Solid State Science and Technology.  6 (2016)  1 - p. P14-P20 , 2016
Link: https://doi.org/10.1149/..
 
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2

Growth and Processing Defects in CMOS Homo- and Hetero-Epit..:

Simoen, Eddy ; Bargallo Gonzalez, Mireia ; Eneman, Geert...
ECS Transactions.  34 (2011)  1 - p. 761-768 , 2011
Link: https://doi.org/10.1149/..
 
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3

Selective Epitaxial Growth: Trends in a Modern Transistor D..:

Hikavyy, Andriy Y. ; Vanherle, Wendy ; Dekoster, Johan...
ECS Transactions.  34 (2011)  1 - p. 455-465 , 2011
Link: https://doi.org/10.1149/..
 
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4

Material Aspects and Challenges for SOI FinFET Integration:

Van Dal, Mark J. ; Vellianitis, Georgios ; Duffy, Ray...
ECS Transactions.  13 (2008)  1 - p. 223-234 , 2008
Link: https://doi.org/10.1149/..
 
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5

Application Of HCl Gas Phase Etch In The Production Of Nove..:

Hikavyy, Andriy Y. ; Rooyackers, Rita ; Verheyen, Peter...
ECS Transactions.  13 (2008)  1 - p. 329-335 , 2008
Link: https://doi.org/10.1149/..
 
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6

Processing technologies for advanced Ge devices:

Loo, R ; Hikavyy, A.Y ; Witters, L...
Loo, R, Hikavyy, A.Y, Witters, L, Schulze, A, Arimura, H, Cott, D, Mitard, J, Porret, C, Mertens, H, Ryan, P, Wall, J, Matney, K, Wormington, M, Favia, P, Richard, O, Bender, H, Thean, A, Horiguchi, N, Mocuta, D, Collaert, N (2017). Processing technologies for advanced Ge devices. ECS Journal of Solid State Science and Technology 6 (1) : P14-P20. ScholarBank@NUS Repository. https://doi.org/10.1149/2.0301612jss.  , 2017
Link: https://scholarbank.nus...
 
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7

Comprehensive 300 mm process for Silicon spin qubits with m..:

, In: 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits),
Elsayed, A. ; Godfrin, C. ; Dumoulin Stuyck, N.I.... - p. 1-2 , 2023
Link: https://doi.org/10.23919..
 
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8

Nanosheet-based Complementary Field-Effect Transistors (CFE..:

, In: 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits),
Mertens, H. ; Hosseini, M. ; Chiarella, T.... - p. 1-2 , 2023
Link: https://doi.org/10.23919..
 
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9

Scaled FinFETs Connected by Using Both Wafer Sides for Rout..:

, In: 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits),
Veloso, A. ; Jourdain, A. ; Radisic, D.... - p. 284-285 , 2022
Link: https://doi.org/10.1109/..
 
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10

Forksheet FETs with Bottom Dielectric Isolation, Self-Align..:

, In: 2022 International Electron Devices Meeting (IEDM),
Mertens, H. ; Ritzenthaler, R. ; Oniki, Y.... - p. 23.1.1-23.1.4 , 2022
Link: https://doi.org/10.1109/..
 
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11

Comparison of Electrical Performance of Co-Integrated Forks..:

, In: 2021 IEEE International Electron Devices Meeting (IEDM),
Ritzenthaler, R. ; Mertens, H. ; Eneman, G.... - p. 26.2.1-26.2.4 , 2021
Link: https://doi.org/10.1109/..
 
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12

First Monolithic Integration of 3D Complementary FET (CFET)..:

, In: 2020 IEEE Symposium on VLSI Technology,
Subramanian, S. ; Hosseini, M. ; Chiarella, T.... - p. 1-2 , 2020
Link: https://doi.org/10.1109/..
 
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13

3D sequential low temperature top tier devices using dopant..:

, In: 2020 IEEE Symposium on VLSI Technology,
Vandooren, A. ; Wu, Z. ; Parihar, N.... - p. 1-2 , 2020
Link: https://doi.org/10.1109/..
 
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14

Epitaxial Growth of (Si)GeSn Source/Drain Layers for Advanc..:

, In: 2019 Compound Semiconductor Week (CSW),
Loo, R. ; Vohra, A. ; Porret, C.... - p. 1-2 , 2019
Link: https://doi.org/10.1109/..
 
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15

Stress analysis of Si1−xGex embedded source/drain junctions:

Bargallo Gonzalez, M. ; Simoen, E. ; Naka, N....
Materials Science in Semiconductor Processing.  11 (2008)  5-6 - p. 285-290 , 2008
Link: https://doi.org/10.1016/..
 
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