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Hormigo, Javier
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1

Advanced Quantization Schemes to Increase Accuracy, Reduce ..:

Garrido, Mario ; Bautista, Víctor Manuel ; Portas, Alejandro.
IEEE Transactions on Circuits and Systems I: Regular Papers.  , 2024
Link: https://doi.org/10.1109/..
 
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2

HUB Meets Posit: Arithmetic Units Implementation:

Murillo, Raul ; Hormigo, Javier ; Barrio, Alberto A. Del.
IEEE Transactions on Circuits and Systems II: Express Briefs.  71 (2024)  1 - p. 440-444 , 2024
Link: https://doi.org/10.1109/..
 
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3

High-Throughput DTW accelerator with minimum area in AMD FP..:

, In: 2023 38th Conference on Design of Circuits and Integrated Systems (DCIS),
Hormigo-Jimenez, Marco ; Hormigo, Javier - p. 1-6 , 2023
Link: https://doi.org/10.1109/..
 
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4

High-Radix Formats for Enhancing Floating-Point FPGA Implem..:

Villalba, Julio ; Hormigo, Javier
Circuits, Systems, and Signal Processing.  41 (2021)  3 - p. 1683-1703 , 2021
Link: https://doi.org/10.1007/..
 
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5

New Results on Non-Normalized Floating-Point Formats:

Gonzalez-Navarro, Sonia ; Hormigo, Javier
IEEE Transactions on Computers.  69 (2020)  12 - p. 1733-1744 , 2020
Link: https://doi.org/10.1109/..
 
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6

Floating–Point Fused Multiply–Add under HUB Format:

, In: 2020 IEEE 27th Symposium on Computer Arithmetic (ARITH),
Hormigo, Javier ; Villalba-Moreno, Julio ; Gonzalez-Navarro, Sonia - p. 1-8 , 2020
Link: https://doi.org/10.1109/..
 
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7

Efficient Floating-Point Givens Rotation Unit:

Hormigo, Javier ; Muñoz, Sergio D.
Circuits, Systems, and Signal Processing.  40 (2020)  5 - p. 2419-2442 , 2020
Link: https://doi.org/10.1007/..
 
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8

Reproducible Summation Under HUB Format:

, In: 2019 IEEE 26th Symposium on Computer Arithmetic (ARITH),
Villalba-Moreno, Julio ; Hormigo, Javier ; Jaime, Francisco - p. 38-45 , 2019
Link: https://doi.org/10.1109/..
 
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9

Designing a Project for Learning Industry 4.0 by Applying I..:

Hormigo, Javier ; Rodriguez, Andres
IEEE Revista Iberoamericana de Tecnologias del Aprendizaje.  14 (2019)  2 - p. 58-65 , 2019
Link: https://doi.org/10.1109/..
 
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10

Unbiased Rounding for HUB Floating-Point Addition:

Villalba-Moreno, Julio ; Hormigo, Javier ; Gonzalez-Navarro, Sonia
IEEE Transactions on Computers.  67 (2018)  9 - p. 1359-1365 , 2018
Link: https://doi.org/10.1109/..
 
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11

Measuring Improvement When Using HUB Formats to Implement F..:

Hormigo, Javier ; Villalba, Julio
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  24 (2016)  6 - p. 2369-2377 , 2016
Link: https://doi.org/10.1109/..
 
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12

Self-Reconfigurable Constant Multiplier for FPGA:

Hormigo, Javier ; Caffarena, Gabriel ; Oliver, Juan P..
ACM Transactions on Reconfigurable Technology and Systems (TRETS).  6 (2013)  3 - p. 1-17 , 2013
Link: https://dl.acm.org/doi/1..
 
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13

Self-Reconfigurable Constant Multiplier for FPGA:

Hormigo, Javier ; Caffarena, Gabriel ; Oliver, Juan P..
ACM Transactions on Reconfigurable Technology and Systems.  6 (2013)  3 - p. 1-17 , 2013
Link: https://doi.org/10.1145/..
 
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14

A study of decimal left shifters for binary numbers:

Gonzalez-Navarro, Sonia ; Hormigo, Javier ; Schulte, Michael J.
Information and Computation.  216 (2012)  - p. 47-56 , 2012
Link: https://doi.org/10.1016/..
 
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15

High-Speed Algorithms and Architectures for Range Reduction..:

Jaime, Francisco J. ; Sanchez, Miguel A. ; Hormigo, Javier..
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  19 (2011)  3 - p. 512-516 , 2011
Link: https://doi.org/10.1109/..
 
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