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Kandula, Bala Sindhuri
7  Ergebnisse:
Personensuche X
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1

Implementation of Square Architecture Based on Yavadunam Su..:

, In: Advances in Automation, Signal Processing, Instrumentation, and Control; Lecture Notes in Electrical Engineering,
Kandula, Bala Sindhuri ; Kavya Kiran, Y. ; Udaya Kumar, N.. - p. 1081-1089 , 2021
Link: https://doi.org/10.1007/..
 
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2

Design of area efficient VLSI architecture for carry select..:

Kandula, Bala Sindhuri ; Kalluru, Padma Vasavi ; Inty, Santi Prabha
Computational Intelligence.  37 (2020)  3 - p. 1155-1165 , 2020
Link: https://doi.org/10.1111/..
 
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3

Area Efficient VLSI Architecture for Square Root Carry Sele..:

Kandula, Bala Sindhuri ; Vasavi, K. Padma ; Prabha, I. Santi
Procedia Computer Science.  89 (2016)  - p. 640-650 , 2016
Link: https://doi.org/10.1016/..
 
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4

Design of 16-Bit Vedic Multiplier Using Modified Logic Gate..:

, In: Lecture Notes in Electrical Engineering; VLSI, Microwave and Wireless Technologies,
Rupa Lakshmi, K. ; Bala Sindhuri, Kandula ; Mani Kumar, K.. - p. 65-72 , 2022
Link: https://doi.org/10.1007/..
 
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5

High Speed Efficient Three Operand Adder:

, In: Lecture Notes in Electrical Engineering; Advances in Signal Processing, Embedded Systems and IoT,
Udaya Kumar, N. ; Bala Sindhuri, K. ; Harsha Varma, S. S.... - p. 695-705 , 2023
Link: https://doi.org/10.1007/..
 
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6

VLSI Implementation of FIR Filter Using Different Addition ..:

, In: Soft Computing Systems; Communications in Computer and Information Science,
Udaya Kumar, N. ; Subbalakshmi, U. ; Surya Priya, B.. - p. 483-490 , 2018
Link: https://doi.org/10.1007/..
 
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7

Performance Evaluation of Vedic Multiplier Using Multiplexe..:

, In: Lecture Notes in Electrical Engineering; Microelectronics, Electromagnetics and Telecommunications,
Udaya Kumar, N. ; Bala Sindhuri, K. ; Subbalakshmi, U.. - p. 349-356 , 2018
Link: https://doi.org/10.1007/..
 
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