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X
Keezer, D.C.
77  Ergebnisse:
Personensuche X
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1

Jitter Reduction for Multi-GHZ ATE Up to 20 GHZ:

, In: 2024 Conference of Science and Technology for Integrated Circuits (CSTIC),
Keezer, D.C. ; Minier, D. ; Li, H. - p. 1-4 , 2024
Link: https://doi.org/10.1109/..
 
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2

Stretching the limits of FPGA SerDes for enhanced ATE perfo..:

, In: Proceedings of the Conference on Design, Automation and Test in Europe,
Majid, A. M. ; Keezer, D. C. - p. 202-207 , 2010
Link: https://dl.acm.org/doi/1..
 
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3

Variable delay of multi-gigahertz digital signals for deske..:

, In: Proceedings of the conference on Design, automation and test in Europe,
Keezer, D. C. ; Minier, D. ; Ducharme, P. - p. 1486-1491 , 2008
Link: https://dl.acm.org/doi/1..
 
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4

MEMS Switches and SiGe Logic for Multi‐GHz Loopback Testing:

Keezer, D. C. ; Minier, D. ; Ducharme, P....
VLSI Design.  2008 (2008)  1 - p. , 2008
Link: https://doi.org/10.1155/..
 
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5

Method for reducing jitter in multi-gigahertz ATE:

, In: Proceedings of the conference on Design, automation and test in Europe,
Keezer, D. C. ; Minier, D. ; Ducharme, P. - p. 701-706 , 2007
Link: https://dl.acm.org/doi/1..
 
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6

Co-development of test electronics and PCI Express interfac..:

, In: 2007 IEEE International Test Conference,
Gray, C.E. ; Liboiron-Ladouceur, O. ; Keezer, D.C.. - p. None , 2007
Link: https://doi.org/10.1109/..
 
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7

Source-synchronous testing of multilane PCI Express and Hyp..:

Keezer, D.C. ; Minier, D. ; Ducharme, P.
IEEE Design & Test of Computers.  23 (2006)  1 - p. 46-57 , 2006
Link: https://doi.org/10.1109/..
 
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8

Low-Cost Multi-Gigahertz Test Systems Using CMOS FPGAs and ..:

, In: Proceedings of the conference on Design, Automation and Test in Europe - Volume 1,
Keezer, D. C. ; Gray, C. ; Majid, A.. - p. 152-157 , 2005
Link: https://dl.acm.org/doi/1..
 
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9

Multiplexing ATE channels for production testing at 2.5 Gbp:

Keezer, D.C. ; Minier, D. ; Caron, M.-C.
IEEE Design and Test of Computers.  21 (2004)  4 - p. 288-301 , 2004
Link: https://doi.org/10.1109/..
 
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10

An architecture for WSI rapid prototyping:

Jain, V.K. ; Hikawa, H. ; Keezer, D.C.
Computer.  25 (1992)  4 - p. 71-75 , 1992
Link: https://doi.org/10.1109/..
 
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11

Wafer Scale Integration: A university perspective:

Jain, V. K. ; Landis, D. L. ; Keezer, D. C...
Journal of VLSI signal processing systems for signal, image and video technology.  2 (1991)  4 - p. 253-269 , 1991
Link: https://doi.org/10.1007/..
 
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12

Erratum to: Wafer Scale Integration: A university perspecti..:

Jain, V. K. ; Landis, D. L. ; Keezer, D. C...
Journal of VLSI signal processing systems for signal, image and video technology.  3 (1991)  4 - p. III-III , 1991
Link: https://doi.org/10.1007/..
 
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13

A Framework for Design of Self-Repairing Digital Systems:

, In: 2019 IEEE International Test Conference (ITC),
Yang, Jingchi ; Keezer, David C. - p. 1-10 , 2019
Link: https://doi.org/10.1109/..
 
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14

Efficient Built-In Test and Calibration of High Speed Seria..:

Moon, Thomas ; Choi, Hyun Woo ; Keezer, David C..
Journal of Electronic Testing.  35 (2019)  6 - p. 809-822 , 2019
Link: https://doi.org/10.1007/..
 
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15

A chip-level security framework for assessing sensor data i..:

, In: Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis,
Wehbe, Taimour ; Mooney, Vincent J. ; Keezer, David C. - p. 1-2 , 2018
Link: https://dl.acm.org/doi/1..
 
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