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Kwai, Ding-Ming
167  Ergebnisse:
Personensuche X
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1

Refresh Power Reduction of DRAMs in DNN Systems Using Hybri..:

, In: 2020 IEEE International Test Conference in Asia (ITC-Asia),
Hsieh, Tsung-Fu ; Li, Jin-Fu ; Lai, Jenn-Shiang... - p. 41-46 , 2020
Link: https://doi.org/10.1109/..
 
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2

A channel-sharable built-in self-test scheme for multi-chan..:

, In: Proceedings of the 23rd Asia and South Pacific Design Automation Conference,
Wu, Kuan-Te ; Li, Jin-Fu ; Lo, Chih-Yen... - p. 245-250 , 2018
Link: https://dl.acm.org/doi/1..
 
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3

Implementation of memory stacking on logic controller by us..:

, In: 2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA),
Chen, Shang-Chun ; Tzeng, Pei-Jer ; Hsm, Yu-Chen... - p. 1-2 , 2016
Link: https://doi.org/10.1109/..
 
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4

Application-Independent Testing of 3-D Field Programmable G..:

Peng, Yen-Lin ; Kwai, Ding-Ming ; Chou, Yung-Fa.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  22 (2014)  2 - p. 207-219 , 2014
Link: https://doi.org/10.1109/..
 
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5

Benchmarking for research in power delivery networks of thr..:

, In: Proceedings of the 2013 ACM International symposium on Physical Design,
Luo, Pei-Wen ; Zhang, Chun ; Chang, Yung-Tai... - p. 17-24 , 2013
Link: https://dl.acm.org/doi/1..
 
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6

Low-Cost Error Tolerance Scheme for 3-D CMOS Imagers:

Chang, Hsiu-Ming Chang ; Huang, Jiun-Lang ; Kwai, Ding-Ming..
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  21 (2013)  3 - p. 465-474 , 2013
Link: https://doi.org/10.1109/..
 
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7

In-Situ Method for TSV Delay Testing and Characterization U..:

You, Jhih-Wei ; Huang, Shi-Yu ; Lin, Yu-Hsiang...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  21 (2013)  3 - p. 443-453 , 2013
Link: https://doi.org/10.1109/..
 
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8

An MCT-Based Bit-Weight Extraction Technique for Embedded S..:

Huang, Xuan-Lun ; Huang, Jiun-Lang ; Chen, Hung-I...
Journal of Electronic Testing.  28 (2012)  5 - p. 705-722 , 2012
Link: https://doi.org/10.1007/..
 
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9

Small delay testing for TSVs in 3-D ICs:

, In: Proceedings of the 49th Annual Design Automation Conference,
Huang, Shi-Yu ; Lin, Yu-Hsiang ; Tsai, Kun-Han (Hans)... - p. 1031-1036 , 2012
Link: https://dl.acm.org/doi/1..
 
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10

Yield Enhancement by Bad-Die Recycling and Stacking With Th..:

Chou, Yung-Fa ; Kwai, Ding-Ming ; Wu, Cheng-Wen
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  19 (2011)  8 - p. 1346-1356 , 2011
Link: https://doi.org/10.1109/..
 
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11

A self-testing and calibration method for embedded successi..:

, In: Proceedings of the 16th Asia and South Pacific Design Automation Conference,
Huang, Xuan-Lun ; Kang, Ping-Ying ; Chang, Hsiu-Ming (Sherman)... - p. 713-718 , 2011
Link: https://dl.acm.org/doi/1..
 
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12

An error tolerance scheme for 3D CMOS imagers:

, In: Proceedings of the 47th Design Automation Conference,
Chang, Hsiu-Ming (Sherman) ; Huang, Jiun-Lang ; Kwai, Ding-Ming.. - p. 917-922 , 2010
Link: https://dl.acm.org/doi/1..
 
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13

CAD reference flow for 3D via-last integrated circuits:

, In: Proceedings of the 2010 Asia and South Pacific Design Automation Conference,
Lin, Chang-Tzu ; Kwai, Ding-Ming ; Chou, Yung-Fa.. - p. 187-192 , 2010
Link: https://dl.acm.org/doi/1..
 
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14

Homogeneous integration for 3D IC with TSV:

, In: Proceedings of the 2010 Asia and South Pacific Design Automation Conference,
Kwai, Ding-Ming - p. 546-547 , 2010
Link: https://dl.acm.org/doi/1..
 
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15

Comparing four classes of torus-based parallel architecture..:

Parhami, B. ; Kwai, Ding-Ming
Mathematical and Computer Modelling.  40 (2004)  7-8 - p. 701-720 , 2004
Link: https://doi.org/10.1016/..
 
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