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LARSSON-EDEFORS, P.
29  Ergebnisse:
Personensuche X
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1

Multiplication Acceleration Through Twin Precision:

Sjalander, M. ; Larsson-Edefors, P.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  17 (2009)  9 - p. 1233-1246 , 2009
Link: https://doi.org/10.1109/..
 
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2

Toward architecture-based test-vector generation for timing..:

Eriksson, H. ; Larsson-Edefors, P. ; Eckerbert, D.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  14 (2006)  4 - p. 370-379 , 2006
Link: https://doi.org/10.1109/..
 
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3

Bit-serial, MSB first processing units:

BELLIS, S. J. ; MARNANE, W. P. ; LARSSON-EDEFORS, P.
International Journal of Electronics.  86 (1999)  6 - p. 723-738 , 1999
Link: https://doi.org/10.1080/..
 
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4

FPGA Implementation of Multi-Layer Machine Learning Equaliz..:

, In: 2023 Optical Fiber Communications Conference and Exhibition (OFC),
Liu, Keren ; Borjeson, Erik ; Hager, Christian. - p. 1-3 , 2023
Link: https://doi.org/10.1364/..
 
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5

Field Trial of FPGA-Based Real-Time Sensing Transceiver ove..:

, In: 2023 Optical Fiber Communications Conference and Exhibition (OFC),
Mazur, Mikael ; Wallberg, Dennis ; Dallachiesa, Lauren... - p. 1-3 , 2023
Link: https://doi.org/10.1364/..
 
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6

Fiber-on-Chip: Digital Emulation of Channel Impairments for..:

Borjeson, Erik ; Larsson-Edefors, Per
Journal of Lightwave Technology.  41 (2023)  3 - p. 888-896 , 2023
Link: https://doi.org/10.1109/..
 
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7

Waveform Memory for Real-Time FPGA Test of Fiber-Optic Rece..:

, In: 2022 IEEE Nordic Circuits and Systems Conference (NorCAS),
Sagredo, Rafael Romon ; Borjeson, Erik ; Mirani, Ali.. - p. 1-6 , 2022
Link: https://doi.org/10.1109/..
 
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8

Power-Efficient ASIC Implementation of DSP Algorithms for C..:

, In: 2020 IEEE Photonics Society Summer Topicals Meeting Series (SUM),
Larsson-Edefors, Per ; Borjeson, Erik - p. 1-2 , 2020
Link: https://doi.org/10.1109/..
 
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9

Hardware Considerations for Selection Networks:

, In: 2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC),
Peter, Kenneth ; Svensson, Lars ; Fougstedt, Christoffer. - p. 40-45 , 2019
Link: https://doi.org/10.1109/..
 
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10

Variable-Rate FEC Decoder VLSI Architecture for 400G Rate-A..:

, In: 2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS),
Jain, Vikram ; Fougstedt, Christoffer ; Larsson-Edefors, Per - p. 45-48 , 2019
Link: https://doi.org/10.1109/..
 
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11

Instruction level energy model for the Adapteva Epiphany mu..:

, In: Proceedings of the Computing Frontiers Conference,
Ortiz, Gabriel ; Svensson, Lars ; Alveflo, Erik. - p. 380-384 , 2017
Link: https://dl.acm.org/doi/1..
 
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12

Redesigning a tagless access buffer to require minimal ISA ..:

, In: Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems,
Sanchez, Carlos ; Gavin, Peter ; Moreau, Daniel... - p. 1-10 , 2016
Link: https://dl.acm.org/doi/1..
 
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13

Improving Data Access Efficiency by Using Context-Aware Loa..:

Bardizbanyan, Alen ; Själander, Magnus ; Whalley, David.
ACM SIGPLAN Notices.  50 (2015)  5 - p. 1-10 , 2015
Link: https://doi.org/10.1145/..
 
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14

Improving Data Access Efficiency by Using Context-Aware Loa..:

, In: Proceedings of the 16th ACM SIGPLAN/SIGBED Conference on Languages, Compilers and Tools for Embedded Systems 2015 CD-ROM,
Bardizbanyan, Alen ; Själander, Magnus ; Whalley, David. - p. 1-10 , 2015
Link: https://dl.acm.org/doi/1..
 
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15

Reducing set-associative L1 data cache energy by early load..:

, In: 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE),
Bardizbanyan, Alen ; Sjalander, Magnus ; Whalley, David. - p. 1-4 , 2014
Link: https://doi.org/10.7873/..
 
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