Ich stimme zu, dass diese Seite Cookies verwende. Weitere Informationen finden Sie unter unseren Datenschutzerklärungen .
X
Lacord, J.
150  Ergebnisse:
Personensuche X
?
1

Doped Channel SOI pMOS TCAD Description Including Floating ..:

, In: 2023 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD),
Lacord, J. ; Boutayeb, A. ; Bosch, D.... - p. 69-72 , 2023
Link: https://doi.org/10.23919..
 
?
2

Extracting edge conduction around threshold in mesa-isolate..:

Boutayeb, A. ; Theodorou, C. ; Golanski, D....
Solid-State Electronics.  209 (2023)  - p. 108736 , 2023
Link: https://doi.org/10.1016/..
 
?
3

Pragmatic OxRAM compact model ready to use for design studi..:

Lacord, J. ; Cagli, C. ; Sandrini, J.
Solid-State Electronics.  204 (2023)  - p. 108652 , 2023
Link: https://doi.org/10.1016/..
 
?
4

A cost effective RF-SOI Drain Extended MOS transistor featu..:

, In: 2023 International Electron Devices Meeting (IEDM),
Garros, X. ; Divay, A. ; Lacord, J.... - p. 1-4 , 2023
Link: https://doi.org/10.1109/..
 
?
5

Electrical characterization of SOI pMOS device leakage:

Bosch, D. ; Lheritier, P. ; Guyader, F....
Solid-State Electronics.  208 (2023)  - p. 108740 , 2023
Link: https://doi.org/10.1016/..
 
?
6

SOI pMOS drain leakage understanding based on TCAD and meas..:

, In: 2023 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD),
Bosch, D. ; Lheritier, P. ; Guyader, F.... - p. 65-68 , 2023
Link: https://doi.org/10.23919..
 
?
7

Fabrication of Low-Power RRAM for Stateful Hyperdimensional..:

, In: 2023 International VLSI Symposium on Technology, Systems and Applications (VLSI-TSA/VLSI-DAT),
Dubreuil, T. ; Barraud, S. ; Previtali, B.... - p. 1-2 , 2023
Link: https://doi.org/10.1109/..
 
?
8

Methodology for Active Junction Profile Extraction in thin ..:

, In: 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits),
Frutuoso, T. Mota ; Garros, X. ; Batude, P.... - p. 332-333 , 2022
Link: https://doi.org/10.1109/..
 
?
9

Si/Si0.7Ge0.3 A2RAM nanowires fabrication and characterizat..:

Lacord, J. ; Tcheme Wakam, F. ; Chalupa, Z....
Solid-State Electronics.  193 (2022)  - p. 108294 , 2022
Link: https://doi.org/10.1016/..
 
?
10

3-Tier BSI CIS with 3D Sequential & Hybrid Bonding Enabling..:

, In: 2022 International Electron Devices Meeting (IEDM),
Guyader, F. ; Batude, P. ; Malinge, P.... - p. 37.4.1-37.4.4 , 2022
Link: https://doi.org/10.1109/..
 
?
11

High-resistivity silicon-based substrate using buried PN ju..:

Moulin, M. ; Rack, M. ; Fache, T....
Solid-State Electronics.  194 (2022)  - p. 108301 , 2022
Link: https://doi.org/10.1016/..
 
?
12

3D sequential integration: applications and associated key ..:

, In: 2021 IEEE International Electron Devices Meeting (IEDM),
Batude, P. ; Billoint, O. ; Thuries, S.... - p. 3.2.1-3.2.4 , 2021
Link: https://doi.org/10.1109/..
 
?
13

A Review of Low Temperature Process Modules Leading Up to t..:

Fenouillet-Beranger, C. ; Brunet, L. ; Batude, P....
IEEE Transactions on Electron Devices.  68 (2021)  7 - p. 3142-3148 , 2021
Link: https://doi.org/10.1109/..
 
?
14

Si/Si0.7Ge0.3 A2RAM nanowires fabrication and characterizat..:

, In: 2021 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EuroSOI-ULIS),
Lacord, J. ; Wakam, F. Tcheme ; Chalupa, Z.... - p. 1-4 , 2021
Link: https://doi.org/10.1109/..
 
?
15

Comparative experimental study of junctionless and inversio..:

, In: 2020 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA),
Bosch, D. ; Colinge, J.P. ; Lugo, J.... - p. 126-127 , 2020
Link: https://doi.org/10.1109/..
 
1-15