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Lee, Daeyeal
15  Ergebnisse:
Personensuche X
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1

Machine Learning Prediction for Design and System Technolog..:

Cheng, Chung-Kuan ; Ho, Chia-Tung ; Holtz, Chester..
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  30 (2022)  8 - p. 1059-1072 , 2022
Link: https://doi.org/10.1109/..
 
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2

PROBE2.0: A Systematic Framework for Routability Assessment..:

Cheng, Chung-Kuan ; Kahng, Andrew B. ; Kim, Hayoung...
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.  41 (2022)  5 - p. 1495-1508 , 2022
Link: https://doi.org/10.1109/..
 
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3

Monolithic 3D Semiconductor Footprint Scaling Exploration B..:

Cheng, Chung-Kuan ; Ho, Chia-Tung ; Lee, Daeyeal.
IEEE Access.  10 (2022)  - p. 65971-65981 , 2022
Link: https://doi.org/10.1109/..
 
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4

Multirow Complementary-FET (CFET) Standard Cell Synthesis F..:

Cheng, Chung-Kuan ; Ho, Chia-Tung ; Lee, Daeyeal.
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits.  7 (2021)  1 - p. 43-51 , 2021
Link: https://doi.org/10.1109/..
 
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5

SMT-Based Contention-Free Task Mapping and Scheduling on 2D..:

Lee, Daeyeal ; Lin, Bill ; Cheng, Chung-Kuan
ACM Transactions on Architecture and Code Optimization.  19 (2021)  1 - p. 1-21 , 2021
Link: https://doi.org/10.1145/..
 
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6

Many-Tier Vertical Gate-All-Around Nanowire FET Standard Ce..:

Lee, Daeyeal ; Ho, Chia-Tung ; Kang, Ilgweon...
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits.  7 (2021)  1 - p. 52-60 , 2021
Link: https://doi.org/10.1109/..
 
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7

Complementary-FET (CFET) Standard Cell Synthesis Framework ..:

Cheng, Chung-Kuan ; Ho, Chia-Tung ; Lee, Daeyeal..
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  29 (2021)  6 - p. 1178-1191 , 2021
Link: https://doi.org/10.1109/..
 
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8

Standard-Cell Scaling Framework with Guaranteed Pin-Accessi..:

, In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS),
Cheng, Chung-Kuan ; Lee, Daeyeal ; Park, Dongwon - p. 1-5 , 2020
Link: https://doi.org/10.1109/..
 
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9

SP&R: Simultaneous Placement and Routing framework for stan..:

, In: 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC),
Park, Dongwon ; Lee, Daeyeal ; Kang, Ilgweon... - p. 345-350 , 2020
Link: https://doi.org/10.1109/..
 
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10

A routability-driven complimentary-FET (CFET) standard cell..:

, In: Proceedings of the 39th International Conference on Computer-Aided Design,
Cheng, Chung-Kuan ; Ho, Chia-Tung ; Lee, Daeyeal. - p. 1-8 , 2020
Link: https://dl.acm.org/doi/1..
 
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11

Effects of Angle-of-Attack on the Aeroelastic Characteristi..:

Park, Young-Keun ; Yoo, Jae-Han ; Lee, In.
Journal of Spacecraft and Rockets.  43 (2006)  6 - p. 1419-1422 , 2006
Link: https://doi.org/10.2514/..
 
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12

Logical Reasoning Techniques for VLSI Applications:

Lee, Daeyeal
qt7xp6p3h1.  , 2022
Link: https://escholarship.org..
 
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13

Monolithic 3D Semiconductor Footprint Scaling Exploration B..:

Chung-Kuan Cheng ; Chia-Tung Ho ; Daeyeal Lee.
https://ieeexplore.ieee.org/document/9798831/.  , 2022
Link: https://doi.org/10.1109/..
 
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14

Multirow Complementary-FET (CFET) Standard Cell Synthesis F..:

Chung-Kuan Cheng ; Chia-Tung Ho ; Daeyeal Lee.
https://ieeexplore.ieee.org/document/9466133/.  , 2021
Link: https://doi.org/10.1109/..
 
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15

Many-Tier Vertical Gate-All-Around Nanowire FET Standard Ce..:

Daeyeal Lee ; Chia-Tung Ho ; Ilgweon Kang...
https://ieeexplore.ieee.org/document/9454552/.  , 2021
Link: https://doi.org/10.1109/..
 
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