Lin, Yibo
1356  Ergebnisse:
Personensuche X
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1

LEAPS: Topological-Layout-Adaptable Multi-Die FPGA Placemen..:

Di, Zhixiong ; Tao, Runzhe ; Mai, Jing..
IEEE Transactions on Circuits and Systems I: Regular Papers.  71 (2024)  3 - p. 1259-1272 , 2024
 
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3

Routing-aware Legal Hybrid Bonding Terminal Assignment for ..:

, In: Proceedings of the 2024 International Symposium on Physical Design,
Liu, Siting ; Jiang, Jiaxi ; He, Zhuolun... - p. 75-82 , 2024
 
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4

Barium isotopes in stromatolites through deep-time: A novel..:

Hohl, Simon V. ; Lin, Yi-Bo ; Wei, Hai-Zhen..
Earth and Planetary Science Letters.  632 (2024)  - p. 118639 , 2024
 
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5

An efficient Cd two-stage column system for high-precision ..:

Zhang, Zheyuan ; Li, Tao ; Li, Baichan...
Journal of Analytical Atomic Spectrometry.  39 (2024)  4 - p. 1142-1151 , 2024
 
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7

Multielectrostatic FPGA Placement Considering SLICEL–SLICEM..:

Mai, Jing ; Wang, Jiarui ; Di, Zhixiong.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.  43 (2024)  2 - p. 641-653 , 2024
 
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8

An Efficient Task-Parallel Pipeline Programming Framework:

, In: Proceedings of the International Conference on High Performance Computing in Asia-Pacific Region,
 
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9

Multi-Electrostatics Based Placement for Non-Integer Multip..:

, In: Proceedings of the 2024 International Symposium on Physical Design,
Zhang, Yu ; Pu, Yuan ; Liu, Fangzhou... - p. 161-168 , 2024
 
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10

Imbalanced Large Graph Learning Framework for FPGA Logic El..:

Di, Zhixiong ; Tao, Runzhe ; Chen, Lin..
IEEE Transactions on Circuits and Systems II: Express Briefs.  71 (2024)  4 - p. 2034-2038 , 2024
 
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11

Analytical Die-to-Die 3-D Placement With Bistratal Wireleng..:

Liao, Peiyu ; Zhao, Yuxuan ; Guo, Dawei..
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.  43 (2024)  6 - p. 1624-1637 , 2024
 
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12

Post-layout simulation driven analog circuit sizing:

Gao, Xiaohan ; Zhang, Haoyi ; Ye, Siyuan...
Science China Information Sciences.  67 (2024)  4 - p. , 2024
 
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13

Dynamic Supply Noise Aware Timing Analysis With JIT Machine..:

Chen, Yufei ; Guo, Zizheng ; Wang, Runsheng...
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.  43 (2024)  5 - p. 1511-1524 , 2024
 
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14

IncreMacro: Incremental Macro Placement Refinement:

, In: Proceedings of the 2024 International Symposium on Physical Design,
Pu, Yuan ; Chen, Tinghuan ; He, Zhuolun... - p. 169-176 , 2024
 
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15

Automated Lithography Resolution Enhancement with Deep Lear..:

, In: Proceedings of the Great Lakes Symposium on VLSI 2024,
Liu, Zixi ; Lin, Yibo ; Su, Xiaojing... - p. 592-598 , 2024
 
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