E-LIB Suche - Ergebnisse für: Loi, Igor

1

Scalable Hierarchical Instruction Cache for Ultralow-Power ..:

Chen, Jie ; Loi, Igor ; Flamand, Eric...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 31 (2023) 4 - p. 456-469 , 2023

Link: https://doi.org/10.1109/..

2

Vega: A Ten-Core SoC for IoT Endnodes With DNN Acceleration..:

Rossi, Davide ; Conti, Francesco ; Eggiman, Manuel...
IEEE Journal of Solid-State Circuits. 57 (2022) 1 - p. 127-139 , 2022

Link: https://doi.org/10.1109/..

3

Energy-Efficient Two-level Instruction Cache Design for an ..:

, In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE),

Jie, Chen ; Loi, Igor ; Benini, Luca. - p. 1734-1739 , 2020

Link: https://doi.org/10.23919..

4

Energy-efficient two-level instruction cache design for an ..:

, In: Proceedings of the 23rd Conference on Design, Automation and Test in Europe,

Jie, Chen ; Loi, Igor ; Benini, Luca. - p. 1734-1739 , 2020

Link: https://dl.acm.org/doi/1..

5

The Quest for Energy-Efficient I$ Design in Ultra-Low-Power..:

Loi, Igor ; Capotondi, Alessandro ; Rossi, Davide..
IEEE Transactions on Multi-Scale Computing Systems. 4 (2018) 2 - p. 99-112 , 2018

Link: https://doi.org/10.1109/..

6

Logic-Base Interconnect Design for Near Memory Computing in..:

Azarkhish, Erfan ; Pfister, Christoph ; Rossi, Davide..
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 25 (2017) 1 - p. 210-223 , 2017

Link: https://doi.org/10.1109/..

7

Energy-Efficient Near-Threshold Parallel Computing: The PUL..:

Rossi, Davide ; Pullini, Antonio ; Loi, Igor...
IEEE Micro. 37 (2017) 5 - p. 20-31 , 2017

Link: https://doi.org/10.1109/..

8

A Hybrid Instruction Prefetching Mechanism for Ultra Low-Po..:

Payami, Maryam ; Azarkhish, Erfan ; Loi, Igor.
IEEE Embedded Systems Letters. 9 (2017) 4 - p. 125-128 , 2017

Link: https://doi.org/10.1109/..

9

Near-Threshold RISC-V Core With DSP Extensions for Scalable..:

Gautschi, Michael ; Schiavone, Pasquale Davide ; Traber, Andreas...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 25 (2017) 10 - p. 2700-2713 , 2017

Link: https://doi.org/10.1109/..

10

On-the-fly adaptivity for process networks over shared-memo..:

Tuveri, Giuseppe ; Meloni, Paolo ; Palumbo, Francesca...
Microprocessors and Microsystems. 46 (2016) - p. 240-254 , 2016

Link: https://doi.org/10.1016/..

11

A 60 GOPS/W, −1.8 V to 0.9 V body bias ULP cluster in 28 nm..:

Rossi, Davide ; Pullini, Antonio ; Loi, Igor...
Solid-State Electronics. 117 (2016) - p. 170-184 , 2016

Link: https://doi.org/10.1016/..

12

Curbing the roofline : a scalable and flexible architect..:

, In: Proceedings of the ACM International Conference on Computing Frontiers,

Meloni, Paolo ; Deriu, Gianfranco ; Conti, Francesco... - p. 376-383 , 2016

Link: https://dl.acm.org/doi/1..

13

A Modular Shared L2 Memory Design for 3-D Integration:

Azarkhish, Erfan ; Rossi, Davide ; Loi, Igor.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 23 (2015) 8 - p. 1485-1498 , 2015

Link: https://doi.org/10.1109/..

14

PULP: A Ultra-Low Power Parallel Accelerator for Energy-Eff..:

Conti, Francesco ; Rossi, Davide ; Pullini, Antonio..
Journal of Signal Processing Systems. 84 (2015) 3 - p. 339-354 , 2015

Link: https://doi.org/10.1007/..

15

Exploring multi-banked shared-L1 program cache on ultra-low..:

, In: Proceedings of the 12th ACM International Conference on Computing Frontiers,

Loi, Igor ; Rossi, Davide ; Haugou, Germain.. - p. 1-8 , 2015

Link: https://dl.acm.org/doi/1..