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Mehendale, Mahesh
40  Ergebnisse:
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1

RAMAN: A Reconfigurable and Sparse tinyML Accelerator for I..:

Krishna, Adithya ; Rohit Nudurupati, Srikanth ; Chandana, D. G....
IEEE Internet of Things Journal.  11 (2024)  14 - p. 24831-24845 , 2024
Link: https://doi.org/10.1109/..
 
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2

Live Demonstration: Real-time audio and visual inference on..:

, In: 2024 IEEE International Symposium on Circuits and Systems (ISCAS),
Krishna, Adithya ; Rajesh, Ashwin ; Oleti, Hitesh Pavan... - p. 1-1 , 2024
Link: https://doi.org/10.1109/..
 
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3

Live Demonstration: Audio Inference using Neuromorphic Coch..:

, In: 2023 IEEE Biomedical Circuits and Systems Conference (BioCAS),
Krishna, Adithya ; Oleti, Hitesh Pavan ; Chauhan, Anand... - p. 1-1 , 2023
Link: https://doi.org/10.1109/..
 
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4

A Sparsity-driven tinyML Accelerator for Decoding Hand Kine..:

, In: 2023 IEEE Biomedical Circuits and Systems Conference (BioCAS),
Krishna, Adithya ; Ramanathan, Vignesh ; Yadav, Satyapreet Singh... - p. 1-5 , 2023
Link: https://doi.org/10.1109/..
 
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5

An area-efficient 6T-SRAM based Compute-In-Memory architect..:

, In: 2022 IEEE Custom Integrated Circuits Conference (CICC),
Biswas, Avishek ; Sanghvi, Hetul ; Mehendale, Mahesh. - p. 1-2 , 2022
Link: https://doi.org/10.1109/..
 
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6

DBQ: A Differentiable Branch Quantizer for Lightweight Deep..:

, In: Computer Vision – ECCV 2020; Lecture Notes in Computer Science,
Dbouk, Hassan ; Sanghvi, Hetul ; Mehendale, Mahesh. - p. 90-106 , 2020
Link: https://doi.org/10.1007/..
 
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7

A 1.2 pJ/cycle KHz Timer Circuit for Heavily Duty-Cycled Sy..:

, In: 2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID),
Manikandan, R.R. ; Singhal, Vipul ; Chauhan, Rajat.. - p. 171-176 , 2018
Link: https://doi.org/10.1109/..
 
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8

DA-Based Circuits for Inner-Product Computation:

, In: Arithmetic Circuits for DSP Applications,
Mehendale, Mahesh ; Sharma, Mohit ; Meher, Pramod Kumar - p. 77-112 , 2017
Link: https://doi.org/10.1002/..
 
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9

Session 14 overview: Deep-learning processors:

, In: 2017 IEEE International Solid-State Circuits Conference (ISSCC),
Hashimoto, Takashi ; Mehendale, Mahesh ; Byeong-Gyu Nam - p. 236-237 , 2017
Link: https://doi.org/10.1109/..
 
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10

MicroRefresh : Minimizing Refresh Overhead in DRAM Cache:

, In: Proceedings of the Second International Symposium on Memory Systems,
Gulur, Nagendra ; Govindarajan, R. ; Mehendale, Mahesh - p. 350-361 , 2016
Link: https://dl.acm.org/doi/1..
 
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11

Session 4 overview: Digital processors:

, In: 2016 IEEE International Solid-State Circuits Conference (ISSCC),
Mehendale, Mahesh ; Shin, Luke - p. 70-71 , 2016
Link: https://doi.org/10.1109/..
 
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12

F1: Designing secure systems: Manufacturing, circuits and a..:

, In: 2016 IEEE International Solid-State Circuits Conference (ISSCC),
De, Vivek ; Bernstein, Kerry ; Yoshikawa, Takefumi... - p. 492-494 , 2016
Link: https://doi.org/10.1109/..
 
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13

A Comprehensive Analytical Performance Model of DRAM Caches:

, In: Proceedings of the 6th ACM/SPEC International Conference on Performance Engineering,
Gulur, Nagendra ; Mehendale, Mahesh ; Govindarajan, Ramaswamy - p. 157-168 , 2015
Link: https://dl.acm.org/doi/1..
 
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14

ANATOMY: an analytical model of memory system performance:

Gulur, Nagendra ; Mehendale, Mahesh ; Manikantan, Raman.
ACM SIGMETRICS Performance Evaluation Review.  42 (2014)  1 - p. 505-517 , 2014
Link: https://doi.org/10.1145/..
 
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15

Bi-Modal DRAM Cache : A Scalable and Effective Die-Stack..:

, In: Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture,
Gulur, Nagendra ; Mehendale, Mahesh ; Manikantan, R.. - p. 38-50 , 2014
Link: https://dl.acm.org/doi/1..
 
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