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Meher, Pramod K.
452  Ergebnisse:
Personensuche X
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1

Enhanced Sharpening of CIC Decimation Filters, Implementati..:

Aggarwal, Supriya ; Meher, Pramod K.
Circuits, Systems, and Signal Processing.  41 (2022)  8 - p. 4581-4603 , 2022
Link: https://doi.org/10.1007/..
 
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2

Analysis of Systolic Penalties and Design of Efficient Digi..:

Meher, Bimal K. ; Meher, Pramod K.
Circuits, Systems, and Signal Processing.  38 (2018)  2 - p. 774-790 , 2018
Link: https://doi.org/10.1007/..
 
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3

Efficient approximate core transform and its reconfigurable..:

Jridi, Maher ; Alfalou, Ayman ; Meher, Pramod K.
Journal of Real-Time Image Processing.  17 (2018)  2 - p. 329-339 , 2018
Link: https://doi.org/10.1007/..
 
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4

Concept, Design, and Implementation of Reconfigurable CORDI:

Aggarwal, Supriya ; Meher, Pramod K. ; Khare, Kavita
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  24 (2016)  4 - p. 1588-1592 , 2016
Link: https://doi.org/10.1109/..
 
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5

A Comparison of Integer Cosine and Tchebichef Transforms fo..:

Prattipati, Soni ; Swamy, M. N. S. ; Meher, Pramod K.
Journal of Signal and Information Processing.  6 (2015)  3 - p. 203-216 , 2015
Link: https://doi.org/10.4236/..
 
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6

Area‐delay‐power‐efficient architecture for folded two‐dime..:

Mohanty, Basant Kumar ; Meher, Pramod K.
IET Image Processing.  8 (2014)  6 - p. 345-353 , 2014
Link: https://doi.org/10.1049/..
 
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7

An Efficient Look-up Table-based Approach for Multiplicatio..:

Meher, Bimal K. ; Meher, Pramod K.
Circuits, Systems, and Signal Processing.  32 (2013)  6 - p. 2623-2638 , 2013
Link: https://doi.org/10.1007/..
 
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8

Guest Editorial: Advanced Techniques for Efficient Electron..:

Meher, Pramod K. ; Mohanty, Saraju P. ; Vinod, A. P.
Circuits, Systems, and Signal Processing.  32 (2013)  6 - p. 2539-2541 , 2013
Link: https://doi.org/10.1007/..
 
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9

Improved Comb Filter based Approach for Effective Predictio..:

Meher, Jayakishan ; Meher, Pramod K. ; Dash, Gananath
Journal of Signal and Information Processing.  2 (2011)  2 - p. 88-99 , 2011
Link: https://doi.org/10.4236/..
 
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10

Efficient Systolic Designs for 1- and 2-Dimensional DFT of ..:

Meher, Pramod K. ; Patra, Jagdish C. ; Vinod, A. P.
Journal of Signal Processing Systems.  60 (2009)  1 - p. 1-14 , 2009
Link: https://doi.org/10.1007/..
 
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11

Nonlinear channel equalization for wireless communication s..:

Patra, Jagdish C. ; Meher, Pramod K. ; Chakraborty, Goutam
Signal Processing.  89 (2009)  11 - p. 2251-2262 , 2009
Link: https://doi.org/10.1016/..
 
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12

VLSI Architecture for High-Speed / Low-Power Implementation..:

, In: APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems,
Mohanty, Basant K. ; Meher, Pramod K. - p. None , 2006
Link: https://doi.org/10.1109/..
 
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13

Merged-Cascaded Systolic Array for VLSI Implementation of D..:

, In: APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems,
Meher, Pramod K. - p. None , 2006
Link: https://doi.org/10.1109/..
 
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14

50 Years of FFT Algorithms and Applications:

Kumar, G. Ganesh ; Sahoo, Subhendu K. ; Meher, Pramod Kumar
Circuits, Systems, and Signal Processing.  38 (2019)  12 - p. 5665-5698 , 2019
Link: https://doi.org/10.1007/..
 
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15

CORDIC Circuits:

, In: Arithmetic Circuits for DSP Applications,
Meher, Pramod Kumar ; Valls, Javier ; Juang, Tso-Bing.. - p. 149-185 , 2017
Link: https://doi.org/10.1002/..
 
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