E-LIB Suche - Ergebnisse für: Narendar, Vadthiya

1

A novel step architecture based negative capacitance (SNC) ..:

Padhi, Santosh Kumar ; Narendar, Vadthiya ; Nishad, Atul Kumar
Microelectronics Journal. 146 (2024) - p. 106139 , 2024

Link: https://doi.org/10.1016/..

2

NDR free negative capacitance CGAAFET at 2nm technology nod..:

Kothapally, Ravi ; Narendar, Vadthiya ; Maheshwaram, Satish
Microelectronics Journal. 142 (2023) - p. 106018 , 2023

Link: https://doi.org/10.1016/..

3

Circuit Analysis and Optimization of GAA Nanowire FET Towar..:

Sreenivasulu, V. Bharath ; Narendar, Vadthiya
Silicon. 14 (2022) 16 - p. 10401-10411 , 2022

Link: https://doi.org/10.1007/..

4

Junctionless SOI FinFET with advanced spacer techniques for..:

Sreenivasulu, V. Bharath ; Narendar, Vadthiya
AEU - International Journal of Electronics and Communications. 145 (2022) - p. 154069 , 2022

Link: https://doi.org/10.1016/..

5

On the design of p-channel step-FinFET at sub-10nm node: A ..:

Padhi, Santosh Kumar ; Narendar, Vadthiya ; Nishad, Atul Kumar
Microelectronics Journal. 126 (2022) - p. 105505 , 2022

Link: https://doi.org/10.1016/..

6

Design Insights of Nanosheet FET and CMOS Circuit Applicati..:

Sreenivasulu, V. Bharath ; Narendar, Vadthiya
IEEE Transactions on Electron Devices. 69 (2022) 8 - p. 4115-4122 , 2022

Link: https://doi.org/10.1109/..

7

Junctionless Gate-all-around Nanowire FET with Asymmetric S..:

Sreenivasulu, V. Bharath ; Narendar, Vadthiya
Silicon. 14 (2021) 13 - p. 7461-7471 , 2021

Link: https://doi.org/10.1007/..

8

Performance improvement of spacer engineered n-type SOI Fin..:

Sreenivasulu, V. Bharath ; Narendar, Vadthiya
AEU - International Journal of Electronics and Communications. 137 (2021) - p. 153803 , 2021

Link: https://doi.org/10.1016/..

9

A Comprehensive Analysis of Junctionless Tri-Gate (TG) FinF..:

Sreenivasulu, V. Bharath ; Narendar, Vadthiya
Silicon. 14 (2021) 5 - p. 2009-2021 , 2021

Link: https://doi.org/10.1007/..

10

Design and Temperature Assessment of Junctionless Nanosheet..:

Sreenivasulu, V. Bharath ; Narendar, Vadthiya
Silicon. 14 (2021) 8 - p. 3823-3834 , 2021

Link: https://doi.org/10.1007/..

11

Characterization and optimization of junctionless gate-all-..:

Sreenivasulu, V. Bharath ; Narendar, Vadthiya
Microelectronics Journal. 116 (2021) - p. 105214 , 2021

Link: https://doi.org/10.1016/..

12

Short Channel Effects (SCEs) Based Comparative Study of Dou..:

, In: Lecture Notes in Electrical Engineering; Advances in VLSI, Communication, and Signal Processing,

Narendar, Vadthiya ; Parihar, Richa ; Pandey, Ashutosh Kumar - p. 673-681 , 2019

Link: https://doi.org/10.1007/..

13

Impact of Dimensional Effects on Subsurface Leakage Current..:

, In: Lecture Notes in Electrical Engineering; Advances in VLSI, Communication, and Signal Processing,

Narendar, Vadthiya ; Pandey, Ashutosh Kumar - p. 587-595 , 2019

Link: https://doi.org/10.1007/..

14

Investigation of Short Channel Effects (SCEs) and Analog/RF..:

Narendar, Vadthiya ; Narware, Pallavi ; Bheemudu, V..
Silicon. 12 (2019) 10 - p. 2283-2291 , 2019

Link: https://doi.org/10.1007/..

15

Surface Potential Modeling of Graded-Channel Gate-Stack (GC..:

Narendar, Vadthiya ; Girdhardas, Kalola Ankit
Silicon. 10 (2018) 6 - p. 2865-2875 , 2018

Link: https://doi.org/10.1007/..