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Palomar, Oscar
136  Ergebnisse:
Personensuche X
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1

eProcessor : European, Extendable, Energy-Efficient, Ext..:

, In: Proceedings of the 20th ACM International Conference on Computing Frontiers,
Alvarez, Lluc ; Ruiz, Abraham ; Bigas-Soldevilla, Arnau... - p. 309-314 , 2023
Link: https://dl.acm.org/doi/1..
 
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2

Sargantana: An Academic SoC RISC-V Processor in 22nm FDSOI ..:

, In: 2023 38th Conference on Design of Circuits and Integrated Systems (DCIS),
Doblas, Max ; Candon, Gerard ; Carril, Xavier... - p. 1-6 , 2023
Link: https://doi.org/10.1109/..
 
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3

FAUST: Design and implementation of a pipelined RISC-V vect..:

Kovač, Mate ; Dragić, Leon ; Malnar, Branimir...
Microprocessors and Microsystems.  97 (2023)  - p. 104762 , 2023
Link: https://doi.org/10.1016/..
 
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4

Vitruvius+: An Area-Efficient RISC-V Decoupled Vector Copro..:

Minervini, Francesco ; Palomar, Oscar ; Unsal, Osman...
ACM Transactions on Architecture and Code Optimization.  20 (2023)  2 - p. 1-25 , 2023
Link: https://doi.org/10.1145/..
 
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5

DVINO: A RISC-V Vector Processor Implemented in 65nm Techno..:

, In: 2022 37th Conference on Design of Circuits and Integrated Circuits (DCIS),
Cabo, Guillem ; Candon, Gerard ; Carril, Xavier... - p. 1-6 , 2022
Link: https://doi.org/10.1109/..
 
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6

A RISC-V Simulator and Benchmark Suite for Designing and Ev..:

Ramírez, Cristóbal ; Hernández, César Alejandro ; Palomar, Oscar...
ACM Transactions on Architecture and Code Optimization (TACO).  17 (2020)  4 - p. 1-30 , 2020
Link: https://dl.acm.org/doi/1..
 
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7

A RISC-V Simulator and Benchmark Suite for Designing and Ev..:

Ramírez, Cristóbal ; Hernández, César Alejandro ; Palomar, Oscar...
ACM Transactions on Architecture and Code Optimization.  17 (2020)  4 - p. 1-30 , 2020
Link: https://doi.org/10.1145/..
 
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8

Navigating the Landscape for Real-Time Localization and Map..:

Saeedi, Sajad ; Spink, Tom ; Gorgovan, Cosmin...
Proceedings of the IEEE.  106 (2018)  11 - p. 2020-2039 , 2018
Link: https://doi.org/10.1109/..
 
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9

Vector Processing-Aware Advanced Clock-Gating Techniques fo..:

Ratkovic, Ivan ; Palomar, Oscar ; Stanic, Milan...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  26 (2018)  4 - p. 639-652 , 2018
Link: https://doi.org/10.1109/..
 
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10

An Integrated Vector-Scalar Design on an In-Order ARM Core:

Stanic, Milan ; Palomar, Oscar ; Hayes, Timothy...
ACM Transactions on Architecture and Code Optimization.  14 (2017)  2 - p. 1-26 , 2017
Link: https://doi.org/10.1145/..
 
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11

An Integrated Vector-Scalar Design on an In-Order ARM Core:

Stanic, Milan ; Palomar, Oscar ; Hayes, Timothy...
ACM Transactions on Architecture and Code Optimization (TACO).  14 (2017)  2 - p. 1-26 , 2017
Link: https://dl.acm.org/doi/1..
 
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12

POSTER : An Integrated Vector-Scalar Design on an In-ord..:

, In: Proceedings of the 2016 International Conference on Parallel Architectures and Compilation,
Stanic, Milan ; Palomar, Oscar ; Hayes, Timothy... - p. 447-448 , 2016
Link: https://dl.acm.org/doi/1..
 
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13

Future vector microprocessor extensions for data aggregatio..:

, In: Proceedings of the 43rd International Symposium on Computer Architecture,
Hayes, Timothy ; Palomar, Oscar ; Unsal, Osman.. - p. 418-430 , 2016
Link: https://dl.acm.org/doi/1..
 
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14

A Fully Parameterizable Low Power Design of Vector Fused Mu..:

, In: Proceedings of the 2016 International Symposium on Low Power Electronics and Design,
Ratković, Ivan ; Palomar, Oscar ; Stanić, Milan... - p. 362-367 , 2016
Link: https://dl.acm.org/doi/1..
 
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15

Future vector microprocessor extensions for data aggregatio..:

Hayes, Timothy ; Palomar, Oscar ; Unsal, Osman..
ACM SIGARCH Computer Architecture News.  44 (2016)  3 - p. 418-430 , 2016
Link: https://doi.org/10.1145/..
 
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