E-LIB Suche - Ergebnisse für: Palomar Pérez, Óscar

1

Reusable Verification Environment for a RISC-V Vector Accel..:

Quiroga, Josue ; Genovese, Roberto Ignacio ; Díaz, Ivan...
https://dvcon-proceedings.org/document/reusable-verification-environment-for-a-risc-v-vector-accelerator/. , 2023

Link: http://hdl.handle.net/21..

2

Vitruvius+: An area-efficient RISC-V decoupled vector copro..:

Minervini Minervini, Francesco ; Palomar Pérez, Óscar ; Unsal, Osman Sabri...
https://dl.acm.org/doi/full/10.1145/3575861. , 2023

Link: http://hdl.handle.net/21..

3

Functional verification of a RISC-V vector accelerator:

Jiménez Arador, Víctor ; Rodriguez, Mario ; Dominguez de la Rocha, Marc...
https://ieeexplore.ieee.org/document/9993792. , 2023

Link: http://hdl.handle.net/21..

4

DVINO: A RISC-V vector processor implemented in 65nm techno..:

Cabo Pitarch, Guillem ; Candon, Gerard ; Carril, Xavier...
https://ieeexplore.ieee.org/document/9970128. , 2022

Link: http://hdl.handle.net/21..

5

A RISC-V simulator and benchmark suite for designing and ev..:

Ramírez Lazo, Cristóbal ; Hernández, César Alejandro ; Palomar Pérez, Óscar...
https://dl.acm.org/doi/10.1145/3422667. , 2020

Link: http://hdl.handle.net/21..

6

Vector processing-aware advanced clock-gating techniques fo..:

Ratkovic, Ivan ; Palomar Pérez, Óscar ; Stanic, Milan...
https://ieeexplore.ieee.org/document/8252727/. , 2018

Link: http://hdl.handle.net/21..

7

Navigating the Landscape for Real-time Localisation and Map..:

Nisbet, Andrew ; Mawer, John ; Palomar Perez, Oscar...
Nisbet , A , Mawer , J , Palomar Perez , O , Gorgovan , C , Webb , A , Clarkson , J , Riley , G , Kotselidis , C-E , Luján , M & Furber , S 2018 , ' Navigating the Landscape for Real-time Localisation and Mapping for Robotics, Virtual and Augmented Reality ' , IEEE Proceedings , vol. 106 , no. 11 . https://doi.org/10.1109/JPROC.2018.2856739. , 2018

Link: https://research.manches..

8

Vector processing-aware advanced clock-gating techniques fo..:

Ratkovic, Ivan ; Palomar Pérez, Óscar ; Stanic, Milan...
https://ieeexplore.ieee.org/document/8252727/. , 2018

Link: http://hdl.handle.net/21..

9

An integrated vector-scalar design on an in-order ARM core:

Stanic, Milan ; Palomar Pérez, Óscar ; Hayes, Timothy...
http://dl.acm.org/citation.cfm?id=3075618. , 2017

Link: http://hdl.handle.net/21..

10

An integrated vector-scalar design on an in-order ARM core:

Stanic, Milan ; Palomar Pérez, Óscar ; Hayes, Timothy...
http://dl.acm.org/citation.cfm?id=3075618. , 2017

Link: http://hdl.handle.net/21..

11

POSTER: an integrated vector-scalar design on an in-order A..:

Stanic, Milan ; Palomar Pérez, Óscar ; Hayes, Timothy...
http://dl.acm.org/citation.cfm?id=2974057&dl=ACM&coll=DL. , 2016

Link: http://hdl.handle.net/21..

12

Hardware acceleration for query processing: Leveraging FPGA..:

Arcas Abella, Oriol ; Armejach Sanosa, Adrià ; Hayes, Timothy...
https://ieeexplore.ieee.org/document/7361655. , 2016

Link: http://hdl.handle.net/21..

13

Runtime-aware architectures:

Casas Guix, Marc ; Moreto Planas, Miquel ; Álvarez Martí, Lluc...
http://dx.doi.org/10.1007/978-3-662-48096-0_2. , 2015

Link: http://hdl.handle.net/21..

14

Block-based execution on an integrated vector-scalar in-ord..:

Stanic, Milan ; Palomar Pérez, Óscar
BSC International Doctoral Symposium (3rd: 2016: Barcelona). , 2015

Link: http://hdl.handle.net/21..

15

Runtime-aware architectures:

Casas, Marc ; Moreto Planas, Miquel ; Álvarez Martí, Lluc...
http://dx.doi.org/10.1007/978-3-662-48096-0_2. , 2015

Link: http://hdl.handle.net/21..