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Park, Heechun
92  Ergebnisse:
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1

Design-Technology Co-Optimization with Standard Cell Layout..:

, In: 2024 25th International Symposium on Quality Electronic Design (ISQED),
Yoon, Junghyun ; Park, Heechun - p. 1-7 , 2024
Link: https://doi.org/10.1109/..
 
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2

Comprehensive Physical Design Flow Incorporating 3-D Connec..:

Kim, Suwan ; Park, Heechun
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.  43 (2024)  7 - p. 1944-1956 , 2024
Link: https://doi.org/10.1109/..
 
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3

Graph Neural Network-Based Detailed Placement Optimization ..:

, In: 2024 25th International Symposium on Quality Electronic Design (ISQED),
Lim, Dho Ui ; Park, Heechun - p. 1-6 , 2024
Link: https://doi.org/10.1109/..
 
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4

Timing-Aware Tier Partitioning for 3D ICs with Critical Pat..:

, In: 2024 International Conference on Electronics, Information, and Communication (ICEIC),
Park, Sojung ; Park, Heechun - p. 1-4 , 2024
Link: https://doi.org/10.1109/..
 
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5

DTOC-P: Deep-Learning-Driven Timing Optimization Using Comm..:

Ahn, Jaehoon ; Chang, Kyungjoon ; Choi, Kyu-Myung..
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.  , 2024
Link: https://doi.org/10.1109/..
 
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6

Eliminating Minimum Implant Area Violations With Design Qua..:

Jeong, Eunsol ; Kim, Taewhan ; Park, Heechun
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  31 (2023)  5 - p. 611-621 , 2023
Link: https://doi.org/10.1109/..
 
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7

DTOC: integrating Deep-learning driven Timing Optimization ..:

, In: 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE),
Chang, Kyungjoon ; Ahn, Jaehoon ; Park, Heechun.. - p. 1-6 , 2023
Link: https://doi.org/10.23919..
 
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8

Tightly Linking 3D Via Allocation Towards Routing Optimizat..:

, In: Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design,
Kim, Suwan ; Chung, Sehyeon ; Kim, Taewhan. - p. 1-6 , 2022
Link: https://dl.acm.org/doi/1..
 
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9

Speeding-up neuromorphic computation for neural networks: S..:

Park, Heechun ; Kim, Taewhan
Integration.  82 (2022)  - p. 104-114 , 2022
Link: https://doi.org/10.1016/..
 
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10

Pseudo-3D Physical Design Flow for Monolithic 3D ICs: Compa..:

Park, Heechun ; Ku, Bon Woong ; Chang, Kyungwook..
ACM Transactions on Design Automation of Electronic Systems.  26 (2021)  5 - p. 1-25 , 2021
Link: https://doi.org/10.1145/..
 
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11

Allocation of Always-On State Retention Storage for Power G..:

Kim, Taehwan ; Park, Heechun ; Kim, Taewhan
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  29 (2021)  3 - p. 499-511 , 2021
Link: https://doi.org/10.1109/..
 
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12

Built-in Self-Test and Fault Localization for Inter-Layer V..:

Chaudhuri, Arjun ; Banerjee, Sanmitra ; Kim, Jinwoo...
ACM Journal on Emerging Technologies in Computing Systems.  18 (2021)  1 - p. 1-37 , 2021
Link: https://doi.org/10.1145/..
 
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13

Clock Delivery Network Design and Analysis for Interposer-B..:

Murali, Gauthaman ; Park, Heechun ; Qin, Eric...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  29 (2021)  4 - p. 605-616 , 2021
Link: https://doi.org/10.1109/..
 
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14

Pseudo-3D Approaches for Commercial-Grade RTL-to-GDS Tool F..:

, In: Proceedings of the 2020 International Symposium on Physical Design,
Park, Heechun ; Ku, Bon Woong ; Chang, Kyungwook.. - p. 47-54 , 2020
Link: https://dl.acm.org/doi/1..
 
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15

Architecture, Chip, and Package Codesign Flow for Interpose..:

Kim, Jinwoo ; Murali, Gauthaman ; Park, Heechun...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  28 (2020)  11 - p. 2424-2437 , 2020
Link: https://doi.org/10.1109/..
 
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