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Rao, Nanditha
33  Ergebnisse:
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1

VPU-CIM: A 130nm, 33.98 TOPS/W RRAM based Compute-In-Memory..:

, In: 2024 IEEE International Symposium on Circuits and Systems (ISCAS),
J, Chithambara Moorthii ; Rayapati, Vinay ; Rao, Nanditha. - p. 1-5 , 2024
Link: https://doi.org/10.1109/..
 
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2

SolarAccel: FPGA accelerated 2D cross-correlation of digita..:

Das, Soham ; Rao, Nanditha ; Phanindra, D. V. S..
Journal of Astrophysics and Astronomy.  45 (2024)  1 - p. , 2024
Link: https://doi.org/10.1007/..
 
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3

Hybrid Multi-tile Vector Systolic Architecture for Accelera..:

, In: 2024 IEEE International Symposium on Circuits and Systems (ISCAS),
Shah, Jay ; Rao, Nanditha - p. 1-5 , 2024
Link: https://doi.org/10.1109/..
 
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4

FPGA-based Hardware Software Co-design to Accelerate Brain ..:

, In: 2024 IEEE International Symposium on Circuits and Systems (ISCAS),
Rayapati, Vinay ; Gogireddy, Ravi Kiran Reddy ; Gandi, Ajay Kumar... - p. 1-5 , 2024
Link: https://doi.org/10.1109/..
 
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5

Architectural Exploration of Heterogeneous FPGAs for Perfor..:

, In: 2023 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS),
Mishra, Anubhav ; Rao, Nanditha ; Gore, Ganesh. - p. 232-235 , 2023
Link: https://doi.org/10.1109/..
 
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6

DSEAdd: FPGA based Design Space Exploration for Approximate..:

, In: 2023 24th International Symposium on Quality Electronic Design (ISQED),
Mishra, Archie ; Rao, Nanditha - p. 1-8 , 2023
Link: https://doi.org/10.1109/..
 
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7

An FPGA based Tiled Systolic Array Generator to Accelerate ..:

, In: 2022 25th Euromicro Conference on Digital System Design (DSD),
Devaraddi, Veerendra S ; Rao, Nanditha - p. 316-323 , 2022
Link: https://doi.org/10.1109/..
 
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8

The Characterization of Errors in an FPGA-Based RISC-V Proc..:

Sharma, Jhalak ; Rao, Nanditha
Microelectronics Journal.  123 (2022)  - p. 105392 , 2022
Link: https://doi.org/10.1016/..
 
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9

FastMem: A Fast Architecture-aware Memory Layout Design:

, In: 2022 23rd International Symposium on Quality Electronic Design (ISQED),
Parmar, Alok ; Prasad, Kailash ; Rao, Nanditha. - p. 120-126 , 2022
Link: https://doi.org/10.1109/..
 
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10

An Automated Approach to Compare Bit Serial and Bit Paralle..:

, In: 2022 IEEE International Symposium on Circuits and Systems (ISCAS),
Parmar, Alok ; Prasad, Kailash ; Rao, Nanditha. - p. 2948-2952 , 2022
Link: https://doi.org/10.1109/..
 
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11

Fault Injection Controller Based Framework to Characterize ..:

, In: 2020 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA),
Sharma, Jhalak ; Rao, Nanditha ; Mohamed, Otmane Ait - p. 1-5 , 2020
Link: https://doi.org/10.1109/..
 
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12

A Dynamic Base Data Compression Technique for the Last-Leve..:

, In: Lecture Notes in Electrical Engineering; Modelling, Simulation and Intelligent Computing,
Joshi, Shreya Jayateerth ; Mata, Prashant ; Rao, Nanditha - p. 155-163 , 2020
Link: https://doi.org/10.1007/..
 
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13

A dual threshold voltage modified dynamic power cutoff tech..:

, In: 2019 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT),
Nadella, Sai Dheeraj ; Israel, Alan ; Reddy, Gnaneswara.. - p. 1-5 , 2019
Link: https://doi.org/10.1109/..
 
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14

Matrix metalloproteinases in head and neck cancer: current ..:

Gkouveris, Ioannis ; Nikitakis, Nikolaos ; Aseervatham, Jaya..
Metalloproteinases In Medicine.  4 (2017)  - p. 47-61 , 2017
Link: https://doi.org/10.2147/..
 
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15

MCSim: A Multi-Core Cache Simulator Accelerated on a Resour..:

, In: Proceedings of the Great Lakes Symposium on VLSI 2023,
Shah, Shivani ; Rao, Nanditha P. - p. 155-158 , 2023
Link: https://dl.acm.org/doi/1..
 
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