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Rayapati, Vinay
6  Ergebnisse:
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1

VPU-CIM: A 130nm, 33.98 TOPS/W RRAM based Compute-In-Memory..:

, In: 2024 IEEE International Symposium on Circuits and Systems (ISCAS),
J, Chithambara Moorthii ; Rayapati, Vinay ; Rao, Nanditha. - p. 1-5 , 2024
Link: https://doi.org/10.1109/..
 
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2

Exploring Hardware Activation Function Design: CORDIC Archi..:

, In: 2024 25th International Symposium on Quality Electronic Design (ISQED),
Basavaraju, Mahati ; Rayapati, Vinay ; Rao, Madhav - p. 1-8 , 2024
Link: https://doi.org/10.1109/..
 
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3

POCO: Hardware Characterization of Activation Functions usi..:

, In: 2024 IEEE International Symposium on Circuits and Systems (ISCAS),
Basavaraju, Mahati ; Rayapati, Vinay ; Rao, Madhav - p. 1-5 , 2024
Link: https://doi.org/10.1109/..
 
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4

EBACA: Efficient Bfloat16-based Activation Function Impleme..:

, In: 2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID),
Rayapati, Vinay ; Reddy, Sanampudi GopalaKrishna ; Kumar, Gandi Ajay.. - p. 605-610 , 2024
Link: https://doi.org/10.1109/..
 
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5

FPGA-based Hardware Software Co-design to Accelerate Brain ..:

, In: 2024 IEEE International Symposium on Circuits and Systems (ISCAS),
Rayapati, Vinay ; Gogireddy, Ravi Kiran Reddy ; Gandi, Ajay Kumar... - p. 1-5 , 2024
Link: https://doi.org/10.1109/..
 
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6

High Performance and Energy Efficient AMD and BWAD Pooling ..:

, In: 2023 26th Euromicro Conference on Digital System Design (DSD),
Rayapati, Vinay ; Basavaraju, Mahati ; Rao, Madhav - p. 470-477 , 2023
Link: https://doi.org/10.1109/..
 
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