E-LIB Suche - Ergebnisse für: Renau, Jose

1

A Multi-threaded Fast Hardware Compiler for HDLs:

, In: Proceedings of the 32nd ACM SIGPLAN International Conference on Compiler Construction,

Wang, Sheng-Hong ; Coffman, Hunter James ; Mayer, Kenneth.. - p. 25-36 , 2023

2

Enabling Reduced Simpoint Size Through LiveCache and Detail..:

Renau, Jose ; Liu, Fangping ; Shan, Hongzhang.
BenchCouncil Transactions on Benchmarks, Standards and Evaluations. 2 (2022) 4 - p. 100082 , 2022

Link: https://doi.org/10.1016/..

3

Effective Processor Verification with Logic Fuzzer Enhanced..:

, In: MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture,

Kabylkas, Nursultan ; Thorn, Tommy ; Srinath, Shreesha.. - p. 667-678 , 2021

Link: https://dl.acm.org/doi/1..

4

LiveHD: A Productive Live Hardware Development Flow:

Wang, Sheng-Hong ; Possignolo, Rafael Trapani ; Skinner, Haven Blake.
IEEE Micro. 40 (2020) 4 - p. 67-75 , 2020

Link: https://doi.org/10.1109/..

5

LiveSim: A Fast Hot Reload Simulator for HDLs:

, In: 2020 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS),

Skinner, Haven ; Trapani Possignolo, Rafael ; Wang, Sheng-Hong. - p. 126-135 , 2020

Link: https://doi.org/10.1109/..

6

SMatch : Structural Matching for Fast Resynthesis in FPG..:

, In: Proceedings of the 56th Annual Design Automation Conference 2019,

Possignolo, Rafael Trapani ; Renau, Jose - p. 1-6 , 2019

Link: https://dl.acm.org/doi/1..

7

EMI Architectural Model and Core Hopping:

, In: Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture,

Gorman, Daphne I. ; Possignolo, Rafael Trapani ; Renau, Jose - p. 899-910 , 2019

Link: https://dl.acm.org/doi/1..

8

Automated pipeline transformations with fluid pipelines:

, In: Advanced logic synthesis / André Inácio Reis, Rolf Drechsler, editors

Possignolo, Rafael T. ; Ebrahimi, Elnaz ; Skinner, Haven.. (2018) - p. 125-150

Exemplar: Zentrale:Magazin 02.s.5400

9

GPU NTC Process Variation Compensation With Voltage Stackin:

Trapani Possignolo, Rafael ; Ebrahimi, Elnaz ; Ardestani, Ehsan Khish...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 26 (2018) 9 - p. 1713-1726 , 2018

Link: https://doi.org/10.1109/..

10

Liam : an actor based programming model for HDLs:

, In: Proceedings of the 15th ACM-IEEE International Conference on Formal Methods and Models for System Design,

Skinner, Haven ; Possignolo, Rafael Trapani ; Renau, Jose - p. 185-188 , 2017

Link: https://dl.acm.org/doi/1..

11

LiveSynth : Towards an Interactive Synthesis Flow:

, In: Proceedings of the 54th Annual Design Automation Conference 2017,

Possignolo, Rafael Trapani ; Renau, Jose - p. 1-6 , 2017

Link: https://dl.acm.org/doi/1..

12

Architectural opportunities for novel dynamic EMI shifting ..:

, In: Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture,

Gorman, Daphne I. ; Guthaus, Matthew R. ; Renau, Jose - p. 774-785 , 2017

Link: https://dl.acm.org/doi/1..

13

LiveSynth: Towards an interactive synthesis flow:

, In: 2016 IEEE Hot Chips 28 Symposium (HCS),

Possignolo, Rafael Trapani ; Renau, Jose - p. 1-1 , 2016

Link: https://doi.org/10.1109/..

14

Managing Mismatches in Voltage Stacking with CoreUnfolding:

Ardestani, Ehsan K. ; Possignolo, Rafael Trapani ; Briz, Jose Luis.
ACM Transactions on Architecture and Code Optimization (TACO). 12 (2015) 4 - p. 1-26 , 2015

Link: https://dl.acm.org/doi/1..

15

Message from the program chair:

, In: 2015 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS),

Renau, Jose - p. vii , 2015

Link: https://doi.org/10.1109/..