Ritzenthaler, R.
67  Ergebnisse:
Personensuche X
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1

Compact thermally stable high voltage FinFET with 40 nm tox..:

Spessot, A. ; Matagne, P. ; Arimura, H....
Japanese Journal of Applied Physics.  63 (2024)  3 - p. 03SP12 , 2024
 
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2

Temperature Dependence of Quasi–Ballistic Transport in n–Ty..:

, In: 2024 IEEE Latin American Electron Devices Conference (LAEDC),
Bufler, F. M. ; Vermeersch, B. ; Mishra, S.... - p. 1-4 , 2024
 
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3

CMOS Scaling by Nanosheet Device Architectures and Backside..:

, In: 2024 International VLSI Symposium on Technology, Systems and Applications (VLSI TSA),
Horiguchi, N. ; Mertens, H. ; Ritzenthaler, R.... - p. 1-2 , 2024
 
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5

Reliability challenges in Forksheet Devices: (Invited Paper:

, In: 2023 IEEE International Reliability Physics Symposium (IRPS),
Bury, E. ; Vandemaele, M. ; Franco, J.... - p. 1-8 , 2023
 
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6

Novel Low Thermal Budget CMOS RMG: Performance and Reliabil..:

Franco, J. ; Arimura, H. ; de Marneffe, J.-F....
IEEE Transactions on Electron Devices.  70 (2023)  12 - p. 6658-6664 , 2023
 
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7

Novel Low Thermal Budget CMOS RMG: Performance and Reliabil..:

, In: 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits),
Franco, J. ; Arimura, H. ; de Marneffe, J.-F.... - p. 1-2 , 2023
 
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8

Forksheet FETs with Bottom Dielectric Isolation, Self-Align..:

, In: 2022 International Electron Devices Meeting (IEDM),
Mertens, H. ; Ritzenthaler, R. ; Oniki, Y.... - p. 23.1.1-23.1.4 , 2022
 
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9

High Performance Thermally Resistant FinFETs DRAM Periphera..:

, In: 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits),
Ritzenthaler, R. ; Capogreco, E. ; Dupuy, E.... - p. 306-307 , 2022
 
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10

FinFETs with Thermally Stable RMG Gate Stack for Future DRA..:

, In: 2022 International Electron Devices Meeting (IEDM),
Capogreco, E. ; Arimura, H. ; Ritzenthaler, R.... - p. 26.2.1-26.2.4 , 2022
 
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11

Comparison of Electrical Performance of Co-Integrated Forks..:

, In: 2021 IEEE International Electron Devices Meeting (IEDM),
Ritzenthaler, R. ; Mertens, H. ; Eneman, G.... - p. 26.2.1-26.2.4 , 2021
 
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12

Buried Power Rail Integration with Si FinFETs for CMOS Scal..:

, In: 2020 IEEE Symposium on VLSI Technology,
Gupta, A. ; Mertens, H. ; Tao, Z.... - p. 1-2 , 2020
 
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13

Impact of Fin Height on Bias Temperature Instability of Mem..:

, In: 2019 IEEE International Integrated Reliability Workshop (IIRW),
 
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14

3D-carrier Profiling and Parasitic Resistance Analysis in V..:

, In: 2019 IEEE International Electron Devices Meeting (IEDM),
Eyben, P. ; Machillot, J. ; Kim, M.... - p. 11.3.1-11.3.4 , 2019
 
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15

Low-Frequency Noise Assessment of Work Function Engineering..:

Claeys, C. ; Ritzenthaler, R. ; Schram, T....
ECS Journal of Solid State Science and Technology.  8 (2019)  2 - p. N25-N31 , 2019
 
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