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Ryu, Yesin
6  Ergebnisse:
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1

Native DRAM Cache: Re-architecting DRAM as a Large-Scale Ca..:

, In: 2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA),
Ryu, Yesin ; Kim, Yoojin ; Jung, Giyong.. - p. 1144-1156 , 2024
Link: https://doi.org/10.1109/..
 
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2

A 16 GB 1024 GB/s HBM3 DRAM With Source-Synchronized Bus De..:

Ryu, Yesin ; Ahn, Sung-Gi ; Lee, Jae Hoon...
IEEE Journal of Solid-State Circuits.  58 (2023)  4 - p. 1051-1061 , 2023
Link: https://doi.org/10.1109/..
 
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3

A 16 GB 1024 GB/s HBM3 DRAM with On-Die Error Control Schem..:

, In: 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits),
Ryu, Yesin ; Kwon, Young-Cheon ; Lee, Jae Hoon... - p. 130-131 , 2022
Link: https://doi.org/10.1109/..
 
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4

HBM3 RAS: Enhancing Resilience at Scale:

Gurumurthi, Sudhanva ; Lee, Kijun ; Jang, Munseon...
IEEE Computer Architecture Letters.  20 (2021)  2 - p. 158-161 , 2021
Link: https://doi.org/10.1109/..
 
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5

22.1 A 1.1V 16GB 640GB/s HBM2E DRAM with a Data-Bus Window-..:

, In: 2020 IEEE International Solid- State Circuits Conference - (ISSCC),
Oh, Chi-Sung ; Chun, Ki Chul ; Byun, Young-Yong... - p. 330-332 , 2020
Link: https://doi.org/10.1109/..
 
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6

Clock buffer polarity assignment combined with clock tree g..:

, In: Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design,
Ryu, Yesin ; Kim, Taewhan - p. 416-419 , 2008
Link: https://dl.acm.org/doi/1..
 
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