Sadulla, Shaik
11  Ergebnisse:
Personensuche X
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1

Design and analysis of a novel compact quaternary adder:

Lakshmanachari, S. ; Sadulla, Shaik ; Satyanarayana, G. S. R....
International Journal of System Assurance Engineering and Management.  15 (2024)  7 - p. 3076-3087 , 2024
 
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2

State-of-art design: data selectors using quantum-dot cellu..:

Sreevani, Menda ; Vijay, Vallabhuni ; Chaitanya, Kancharapu...
International Journal of System Assurance Engineering and Management.  15 (2023)  3 - p. 1285-1293 , 2023
 
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3

1-bit full adder design using next generation semiconductor..:

Lakshmanachari, S. ; Shaik, Sadulla ; Satyanarayana, G. S. R....
International Journal of System Assurance Engineering and Management.  15 (2023)  3 - p. 950-956 , 2023
 
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4

Design and performance analysis of low power and energy-eff..:

Shaik, Sadulla ; Kanapala, Satish ; Vijay, Vallabhuni.
International Journal of System Assurance Engineering and Management.  14 (2023)  3 - p. 894-902 , 2023
 
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5

Universal Shift Register Designed at Low Supply Voltages in..:

, In: Advanced Techniques for IoT Applications; Lecture Notes in Networks and Systems,
 
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9

Circuit and Architectural Co-design for Reliable Adder Cell..:

, In: 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID),
 
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11

High secure buffer based physical unclonable functions (PUF..:

Shaik, Sadulla ; Kurra, Anil Kumar ; Surendar, A
http://journal.uad.ac.id/index.php/TELKOMNIKA/article/view/10436/6024.  , 2019
 
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