E-LIB Suche - Ergebnisse für: Saiz-Adalid, Luis J.

1

A Hybrid Technique Based on ECC and Hardened Cells for Tole..:

Gil-Tomás, Daniel ; Saiz-Adalid, Luis J. ; Gracia-Morán, Joaquín..
IEEE Access. 12 (2024) - p. 70662-70675 , 2024

2

Improving Error Correction Codes for Multiple-Cell Upsets i..:

Gracia-Moran, Joaquin ; Saiz-Adalid, Luis J. ; Gil-Tomas, Daniel.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 26 (2018) 10 - p. 2132-2142 , 2018

Link: https://doi.org/10.1109/..

3

A Proposal of an ECC-based Adaptive Fault-Tolerant Mechanis..:

Gracia-Morán, Joaquín ; Saiz-Adalid, Luis-J. ; Baraza-Calvo, J.-Carlos..
IEEE Latin America Transactions. 22 (2024) 5 - p. 418-427 , 2024

Link: https://doi.org/10.1109/..

4

Zero-Space In-Weight and In-Bias Protection for Floating-Po..:

, In: 2024 19th European Dependable Computing Conference (EDCC),

Ruiz, Juan Carlos ; de Andres, David ; Saiz-Adalid, Luis Jose. - p. 89-96 , 2024

Link: https://doi.org/10.1109/..

5

Reducing the Overhead of BCH Codes: New Double Error Correc..:

Saiz-Adalid, Luis-J. ; Gracia-Morán, Joaquín ; Gil-Tomás, Daniel..
Electronics. 9 (2020) 11 - p. 1897 , 2020

Link: https://doi.org/10.3390/..

6

Proposal of an Adaptive Fault Tolerance Mechanism to Tolera..:

Baraza-Calvo, J.-Carlos ; Gracia-Morán, Joaquín ; Saiz-Adalid, Luis-J...
Electronics. 9 (2020) 12 - p. 2074 , 2020

Link: https://doi.org/10.3390/..

7

Ultrafast Codes for Multiple Adjacent Error Correction and ..:

Saiz-Adalid, Luis-J. ; Gracia-Moran, Joaquin ; Gil-Tomas, Daniel..
IEEE Access. 7 (2019) - p. 151131-151143 , 2019

Link: https://doi.org/10.1109/..

8

MCU Tolerance in SRAMs Through Low-Redundancy Triple Adjace..:

Saiz-Adalid, Luis-J. ; Reviriego, Pedro ; Gil, Pedro..
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 23 (2015) 10 - p. 2332-2336 , 2015

Link: https://doi.org/10.1109/..

9

Ultrafast Single Error Correction Codes for Protecting Proc..:

, In: 2015 11th European Dependable Computing Conference (EDCC),

Saiz-Adalid, Luis-J. ; Gil, Pedro ; Gracia-Moran, Joaquin.. - p. 144-154 , 2015

Link: https://doi.org/10.1109/..

10

Analyzing the Impact of Intermittent Faults on Microprocess..:

Gil-Tomas, Daniel ; Gracia-Moran, Joaquin ; Baraza-Calvo, J.-Carlos..
IEEE Design & Test of Computers. 29 (2012) 6 - p. 66-73 , 2012

Link: https://doi.org/10.1109/..

11

Studying the effects of intermittent faults on a microcontr..:

Gil-Tomás, Daniel ; Gracia-Morán, Joaquín ; Baraza-Calvo, J.-Carlos..
Microelectronics Reliability. 52 (2012) 11 - p. 2837-2846 , 2012

Link: https://doi.org/10.1016/..

12

Design, Implementation and Evaluation of a Low Redundant Er..:

Gracia-Morán, Joaquín ; Saiz Adalid, Luis J. ; Baraza Calvo, Juan Carlos..
IEEE Latin America Transactions. 19 (2021) 11 - p. 1903-1911 , 2021

Link: https://doi.org/10.1109/..

13

Adaptive Mechanism to Tolerate Intermittent Faults:

Gracia-Morán, Joaquín ; Saiz-Adalid, Luis ; Gil-Vicente, Pedro..
hal-01226613. , 2015

Link: https://hal.archives-ouv..

14

Design, Implementation and Evaluation of a Low Redundant Er..:

Gracia-Morán, Joaquín ; Saiz-Adalid, Luis-J ; Baraza-Calvo, Juan-Carlos..
info:eu-repo/grantAgreement/UPV//200190032/. , 2021

Link: http://hdl.handle.net/10..

15

Reducing the Overhead of BCH Codes: New Double Error Correc..:

Saiz-Adalid, Luis-J ; Gracia-Morán, Joaquín ; Gil Tomás, Daniel Antonio..
Electronics. , 2020

Link: http://hdl.handle.net/10..