Schuddinck, P.
18  Ergebnisse:
Personensuche X
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1

CMOS Scaling by Nanosheet Device Architectures and Backside..:

, In: 2024 International VLSI Symposium on Technology, Systems and Applications (VLSI TSA),
Horiguchi, N. ; Mertens, H. ; Ritzenthaler, R.... - p. 1-2 , 2024
 
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2

PPA and Scaling Potential of Backside Power Options in N2 a..:

, In: 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits),
Yang, S. ; Schuddinck, P. ; Garcia-Bardon, M.... - p. 1-2 , 2023
 
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3

Buried Interconnects for Sub-5 nm SRAM Design:

Mathur, R. ; Bhargava, M. ; Cline, B....
IEEE Transactions on Electron Devices.  69 (2022)  3 - p. 1041-1047 , 2022
 
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4

PPAC of sheet-based CFET configurations for 4 track design ..:

, In: 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits),
Schuddinck, P. ; Bufler, F. M. ; Xiang, Y.... - p. 365-366 , 2022
 
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5

Backside PDN and 2.5D MIMCAP to Double Boost 2D and 3D ICs ..:

, In: 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits),
Chen, R. ; Sisto, G. ; Stucchi, M.... - p. 429-430 , 2022
 
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6

Self-Heating in iN8–iN2 CMOS Logic Cells: Thermal Impact of..:

, In: 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits),
Vermeersch, B. ; Bury, E. ; Xiang, Y.... - p. 371-372 , 2022
 
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7

Extended Scale Length Theory Targeting Low-Dimensional FETs..:

, In: 2021 IEEE International Electron Devices Meeting (IEDM),
Gilardi, C. ; Chehab, B. ; Sisto, G.... - p. 27.3.1-27.3.4 , 2021
 
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9

Virtual Process-Based Spacer & Junction Optimization for an..:

, In: 2020 4th IEEE Electron Devices Technology & Manufacturing Conference (EDTM),
Guissi, S. ; Schram, T. ; Schuddinck, P... - p. 1-4 , 2020
 
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10

Enabling Sub-5nm CMOS Technology Scaling Thinner and Taller:

, In: 2019 IEEE International Electron Devices Meeting (IEDM),
Ryckaert, J. ; Na, M. H. ; Weckx, P.... - p. 29.4.1-29.4.4 , 2019
 
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11

Novel forksheet device architecture as ultimate logic scali..:

, In: 2019 IEEE International Electron Devices Meeting (IEDM),
Weckx, P. ; Gupta, M. ; Oniki, Y.... - p. 36.5.1-36.5.4 , 2019
 
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12

Understanding energy efficiency benefits of carbon nanotube..:

Hills, G ; Bardon, M.G ; Doornbos, G...
Hills, G, Bardon, M.G., Doornbos, G., Yakimets, D., Schuddinck, P., Baert, R., Jang, D., Mattii, L., Sherazi, S.M.Y., Rodopoulos, D.Catthoor, F.b Email Author , Raghavan, P.b Email Author , Shulaker, M.M.f Email Author , Wong, H.-S.P.a Email Author , Mitra, S.a Email Author, Ritzenthaler, R., Lee, C.-S., THEAN VOON YEW, AARON, Radu, I., Spessot, A, Debacker, P., Catthoor, F., Raghavan, P., Shulaker, M.M., Wong, H.-S.P., Mitra, S. (2018-11-01). Understanding energy efficiency benefits of carbon nanotube field-effect transistors for digital VLSI. IEEE Transactions on Nanotechnology 17 (6) : 1259 - 1269. ScholarBank@NUS Repository. https://doi.org/10.1109/TNANO.2018.2871841.  , 2018
 
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14

Influence of the morphology on the magneto-transport proper..:

Das, A. ; Gordon, I. ; Wagner, P....
Journal of Applied Physics.  90 (2001)  3 - p. 1429-1435 , 2001
 
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