Ich stimme zu, dass diese Seite Cookies verwende. Weitere Informationen finden Sie unter unseren Datenschutzerklärungen .
X
Sinha, Arani
24  Ergebnisse:
Personensuche X
?
1

Innovative Practices Track: Session 3 Test and Functional S..:

, In: 2024 IEEE 42nd VLSI Test Symposium (VTS),
Sinha, Arani - p. 1-1 , 2024
Link: https://doi.org/10.1109/..
 
?
2

Innovative Practices Track: Session 2 Silent Data Corruptio:

, In: 2024 IEEE 42nd VLSI Test Symposium (VTS),
Sinha, Arani ; Singh, Adit D. - p. 1-1 , 2024
Link: https://doi.org/10.1109/..
 
?
3

Innovative Practices Track: Session 4 AI Applications in Te..:

, In: 2024 IEEE 42nd VLSI Test Symposium (VTS),
Sinha, Arani ; Carlo, Stefano Di - p. 1-1 , 2024
Link: https://doi.org/10.1109/..
 
?
4

Maximizing Stress Coverage by Novel DFT Techniques and Rela..:

, In: 2023 IEEE International Test Conference (ITC),
Sinha, Arani ; Colon-Bonet, Glenn ; Fahy, Michael... - p. 56-59 , 2023
Link: https://doi.org/10.1109/..
 
?
5

Innovative Practices Track: Silent Data Errors:

, In: 2022 IEEE 40th VLSI Test Symposium (VTS),
Sinha, Arani - p. 1-1 , 2022
Link: https://doi.org/10.1109/..
 
?
6

Using Fault Detection Tests to Produce Diagnostic Tests Tar..:

, In: 2022 IEEE 31st Asian Test Symposium (ATS),
Addepalli, Hari ; Pomeranz, Irith ; Amyeen, Enamul... - p. 120-125 , 2022
Link: https://doi.org/10.1109/..
 
?
7

Innovative Practices Track: Next Generation Test Standards:

, In: 2022 IEEE 40th VLSI Test Symposium (VTS),
Sinha, Arani - p. 1-1 , 2022
Link: https://doi.org/10.1109/..
 
?
8

Multi-die Parallel Test Fabric for Scalability and Pattern ..:

, In: 2022 IEEE International Test Conference (ITC),
Sinha, Arani ; Cho, Yonsang ; Easter, Jon. - p. 249-257 , 2022
Link: https://doi.org/10.1109/..
 
?
9

Synergies Between Delay Test and Post-silicon Speed Path Va..:

, In: 2021 IEEE European Test Symposium (ETS),
Ray, Sandip ; Sinha, Arani - p. 1-4 , 2021
Link: https://doi.org/10.1109/..
 
?
10

SAT-ATPG Generated Multi-Pattern Scan Tests for Cell Intern..:

, In: 2020 IEEE International Test Conference (ITC),
Pandey, Sujay ; Liao, Zhiwei ; Nandi, Shreyas... - p. 1-10 , 2020
Link: https://doi.org/10.1109/..
 
?
11

Characterization of Library Cells for Open-circuit Defect E..:

, In: 2019 IEEE International Test Conference (ITC),
Pandey, Sujay ; Gupta, Sanya ; L., Madhu Sudhan... - p. 1-10 , 2019
Link: https://doi.org/10.1109/..
 
?
12

Layout Resynthesis by Applying Design-for-manufacturability..:

Wang, Naixing ; Pomeranz, Irith ; Reddy, Sudhakar M...
ACM Transactions on Design Automation of Electronic Systems (TODAES).  24 (2019)  4 - p. 1-19 , 2019
Link: https://dl.acm.org/doi/1..
 
?
13

Layout Resynthesis by Applying Design-for-manufacturability..:

Wang, Naixing ; Pomeranz, Irith ; Reddy, Sudhakar M...
ACM Transactions on Design Automation of Electronic Systems.  24 (2019)  4 - p. 1-19 , 2019
Link: https://doi.org/10.1145/..
 
?
14

Innovative practices session 1C screening for layout sensit..:

, In: 2017 IEEE 35th VLSI Test Symposium (VTS),
Sinha, Arani ; Chaudhary, Nitin - p. 1-1 , 2017
Link: https://doi.org/10.1109/..
 
?
15

Special session 8C: Panel EDA for analog DFT/ATPG – will So..:

, In: 2010 28th VLSI Test Symposium (VTS),
Sinha, Arani - p. 259-259 , 2010
Link: https://doi.org/10.1109/..
 
1-15