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Song, Taigon
29  Ergebnisse:
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1

FS2K: A Forksheet FET Technology Library and a Study of VLS..:

, In: 2024 IEEE International Symposium on Circuits and Systems (ISCAS),
Shin, Yunjeong ; Park, Daehyeok ; Koh, Dohun... - p. 1-5 , 2024
Link: https://doi.org/10.1109/..
 
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2

Design Technology Co-Optimization and Time-Efficient Verifi..:

Jeong, Jaehoon ; Shin, Yunjeong ; Lee, Hyundong...
IEEE Access.  12 (2024)  - p. 97557-97571 , 2024
Link: https://doi.org/10.1109/..
 
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3

Cache Register Sharing Structure for Channel-level Near-mem..:

, In: 2023 24th International Symposium on Quality Electronic Design (ISQED),
Kim, Hyunwoo ; Lee, Hyundong ; Kim, Jongbeom... - p. 1-6 , 2023
Link: https://doi.org/10.1109/..
 
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4

High-throughput PIM (Processing in-Memory) for DRAM using B..:

, In: 2023 20th International SoC Design Conference (ISOCC),
Lee, Hyunsoo ; Lee, Hyundong ; Shin, Minseung... - p. 101-102 , 2023
Link: https://doi.org/10.1109/..
 
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5

Exploration of Ternary Logic Using T-CMOS for Circuit-Level..:

Ko, Jonghyun ; Kim, Jongbeom ; Jeong, Taegam..
IEEE Transactions on Circuits and Systems I: Regular Papers.  70 (2023)  9 - p. 3612-3624 , 2023
Link: https://doi.org/10.1109/..
 
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6

T3L: A Practical Implementation of Tri-Transistor Ternary L..:

Kim, Jongbeom ; Lee, Hyundong ; Ko, Jonghyun..
IEEE Transactions on Circuits and Systems I: Regular Papers.  70 (2023)  12 - p. 4826-4839 , 2023
Link: https://doi.org/10.1109/..
 
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7

Complementary FET (CFET) Standard Cell Design for Low Paras..:

Park, Eunbin ; Song, Taigon
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  31 (2023)  2 - p. 177-187 , 2023
Link: https://doi.org/10.1109/..
 
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8

A Compact Q-Learning-Based Standard Cell Layout Compiler fo..:

, In: 2023 20th International SoC Design Conference (ISOCC),
Shin, MinSeung ; Kim, Jongbeom ; Shin, Yunjeong. - p. 119-120 , 2023
Link: https://doi.org/10.1109/..
 
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9

NS3K: A 3-nm Nanosheet FET Standard Cell Library Developmen..:

Kim, Taehak ; Jeong, Jaehoon ; Woo, Seungmin...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  31 (2023)  2 - p. 163-176 , 2023
Link: https://doi.org/10.1109/..
 
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10

HFGCN: High-speed and Fully-optimized GCN Accelerator:

, In: 2023 24th International Symposium on Quality Electronic Design (ISQED),
Han, MinSeok ; Kim, Jiwan ; Kim, Donggeon... - p. 1-7 , 2023
Link: https://doi.org/10.1109/..
 
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11

A Study on Optimizing Pin Accessibility of Standard Cells i..:

, In: Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design,
Jeong, Jaehoon ; Ko, Jonghyun ; Song, Taigon - p. 1-6 , 2022
Link: https://dl.acm.org/doi/1..
 
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12

Ternary Competitive to Binary: A Novel Implementation of Te..:

, In: 2022 IEEE 52nd International Symposium on Multiple-Valued Logic (ISMVL),
Lee, Hyundong ; Jang, Hyeseung ; Yun, Jihyeong... - p. 21-26 , 2022
Link: https://doi.org/10.1109/..
 
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13

A Convenient Implementation of the Ternary Logic: Using Ant..:

, In: 2022 IEEE 52nd International Symposium on Multiple-Valued Logic (ISMVL),
Kim, Jongbeom ; Kim, Yeji ; Lee, Hyundong... - p. 15-20 , 2022
Link: https://doi.org/10.1109/..
 
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14

Circuit-Level Exploration of Ternary Logic Using Memristors..:

Yang, Jeonggyu ; Lee, Hyundong ; Jeong, Jae Hoon...
IEEE Transactions on Circuits and Systems I: Regular Papers.  69 (2022)  2 - p. 707-720 , 2022
Link: https://doi.org/10.1109/..
 
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15

A Novel Processing Unit and Architecture for Process-In Mem..:

, In: 2022 19th International SoC Design Conference (ISOCC),
Kim, HyunWoo ; Baek, Seungwon ; Song, Jaehong. - p. 127-128 , 2022
Link: https://doi.org/10.1109/..
 
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