Taskin, Baris
140  Ergebnisse:
Personensuche X
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1

High-Speed Phase-Based Computing:

, In: 2024 IEEE International Symposium on Circuits and Systems (ISCAS),
 
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2

Design Automation for Charge Recovery Logic:

, In: 2024 IEEE International Symposium on Circuits and Systems (ISCAS),
 
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3

A 0.45 pJ/bit 20 Gb/s/Wire Parallel Die-to-Die Interface wi..:

, In: 2022 IEEE International Symposium on Circuits and Systems (ISCAS),
Kuttappa, Ragh ; Taskin, Baris - p. 687-691 , 2022
 
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4

Multiphase Digital Low-Dropout Regulators:

Kuttappa, Ragh ; Wang, Longfei ; Kose, Selcuk.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  30 (2022)  1 - p. 40-50 , 2022
 
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6

Resonant Rotary Clock Synchronization with Active and Passi..:

, In: 2022 IEEE International Symposium on Circuits and Systems (ISCAS),
Kuttappa, Ragh ; Taskin, Baris ; Honkote, Vinayak... - p. 692-696 , 2022
 
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7

TSV‐based antenna for on‐chip wireless communication:

Pano, Vasil ; Tekin, Ibrahim ; Liu, Yuqiao..
IET Microwaves, Antennas & Propagation.  14 (2020)  4 - p. 302-307 , 2020
 
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8

Comprehensive Low Power Adiabatic Circuit Design with Reson..:

, In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS),
 
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9

FinFET—Based Low Swing Rotary Traveling Wave Oscillators:

, In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS),
Kuttappa, Ragh ; Taskin, Baris - p. 1-5 , 2020
 
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10

SnackNoC: Processing in the Communication Layer:

, In: 2020 IEEE International Symposium on High Performance Computer Architecture (HPCA),
Sangaiah, Karthik ; Lui, Michael ; Kuttappa, Ragh.. - p. 461-473 , 2020
 
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11

GLSVLSI'19 

proceedings of the 2019 Great Lakes Symposium on VLSI : May...  ACM Conferences;ACM Digital Library
 
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12

On-chip wireless interconnect paradigm:

, In: Proceedings of the 12th International Workshop on Network on Chip Architectures,
Taskin, Baris - p. 1 ff. , 2019
 
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13

Slew Merging Region Propagation for Bounded Slew and Skew C..:

Lerner, Scott ; Taskin, Baris
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  27 (2019)  1 - p. 1-10 , 2019
 
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14

Low Voltage Clock Tree Synthesis with Local Gate Clusters:

, In: Proceedings of the 2019 Great Lakes Symposium on VLSI,
Sitik, Can ; Liu, Weicheng ; Taskin, Baris. - p. 99-104 , 2019
 
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15

SLECTS: Slew-Driven Clock Tree Synthesis:

Liu, Weicheng ; Sitik, Can ; Salman, Emre...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  27 (2019)  4 - p. 864-874 , 2019
 
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