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Titarenko, Larysa
101  Ergebnisse:
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1

Hardware Reduction for FSMs With Extended State Codes:

Barkalov, Alexander ; Titarenko, Larysa ; Mielcarek, Kamil.
IEEE Access.  12 (2024)  - p. 42369-42384 , 2024
Link: https://doi.org/10.1109/..
 
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2

Hardware-Based Implementation of Algorithms for Data Replac..:

Titarenko, Larysa ; Kharchenko, Vyacheslav ; Puidenko, Vadym..
Computers.  13 (2024)  7 - p. 166 , 2024
Link: https://doi.org/10.3390/..
 
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3

Evaluation of Traffic Engineering Routing Models Based on T..:

Barkalov, Alexander ; Lemeshko, Oleksandr ; Persikov, Anatoliy..
Electronics.  13 (2024)  18 - p. 3638 , 2024
Link: https://doi.org/10.3390/..
 
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4

Optimization of the Microprogram Mealy Machine Circuit Base..:

Barkalov, Alexandr ; Titarenko, Larysa ; Golovin, Oleksandr.
Cybernetics and Computer Technologies.  , 2024
Link: https://doi.org/10.34229..
 
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5

Basic Approaches for Reducing Power Consumption in Finite S..:

Barkalov, Alexander ; Titarenko, Larysa ; Bieganowski, Jacek.
Applied Sciences.  14 (2024)  7 - p. 2693 , 2024
Link: https://doi.org/10.3390/..
 
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6

Improving Characteristics of FPGA-Based FSMs Representing S..:

Barkalov, Alexander ; Titarenko, Larysa ; Krzywicki, Kazimierz.
Applied Sciences.  13 (2023)  18 - p. 10200 , 2023
Link: https://doi.org/10.3390/..
 
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7

Hierarchical Queue Management Priority and Balancing Based ..:

Lemeshko, Oleksandr ; Yeremenko, Oleksandra ; Titarenko, Larysa.
Electronics.  12 (2023)  3 - p. 675 , 2023
Link: https://doi.org/10.3390/..
 
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8

Solving Load Balancing Problems in Routing and Limiting Tra..:

Barkalov, Alexander ; Lemeshko, Oleksandr ; Yeremenko, Oleksandra..
Applied Sciences.  13 (2023)  17 - p. 9489 , 2023
Link: https://doi.org/10.3390/..
 
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9

Optimization of a Mealy Automaton Circuit in a Mixed Elemen..:

Barkalov, Alexander ; Titarenko, Larysa ; Golovin, Oleksandr.
Cybernetics and Computer Technologies.  , 2023
Link: https://doi.org/10.34229..
 
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10

Improving the Spatial Characteristics of Three-Level LUT-Ba..:

Barkalov, Alexander ; Titarenko, Larysa ; Mazurkiewicz, Małgorzata.
Electronics.  12 (2023)  5 - p. 1133 , 2023
Link: https://doi.org/10.3390/..
 
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11

Separation of Input Variables for Optimization of the Mealy..:

Barkalov, Alexandr ; Titarenko, Larysa ; Golovin, Oleksandr..
Cybernetics and Computer Technologies.  , 2023
Link: https://doi.org/10.34229..
 
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12

Using a Double-Core Structure to Reduce the LUT Count in FP..:

Barkalov, Alexander ; Titarenko, Larysa ; Krzywicki, Kazimierz
Electronics.  11 (2022)  19 - p. 3089 , 2022
Link: https://doi.org/10.3390/..
 
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13

VLSI-based Logic Synthesis:

, In: Lecture Notes in Electrical Engineering; Logic Synthesis for VLSI-Based Combined Finite State Machines,
Barkalov, Alexander ; Titarenko, Larysa ; Mielcarek, Kamil.. - p. 33-76 , 2022
Link: https://doi.org/10.1007/..
 
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14

ASIC-based Synthesis of CFSMs:

, In: Lecture Notes in Electrical Engineering; Logic Synthesis for VLSI-Based Combined Finite State Machines,
Barkalov, Alexander ; Titarenko, Larysa ; Mielcarek, Kamil.. - p. 77-110 , 2022
Link: https://doi.org/10.1007/..
 
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15

Control Algorithms and Finite State Machines:

, In: Lecture Notes in Electrical Engineering; Logic Synthesis for VLSI-Based Combined Finite State Machines,
Barkalov, Alexander ; Titarenko, Larysa ; Mielcarek, Kamil.. - p. 1-32 , 2022
Link: https://doi.org/10.1007/..
 
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